公开(公告)号：US12160495B2

公开(公告)日：2024-12-03

申请号：US17475200

申请日：2021-09-14

Applicant: Intel Corporation

Inventor： Mark Bordogna ,  Jonathan A. Robinson ,  Srinivasan S. Iyengar

IPC: H04L7/00

Abstract: Examples described herein relate to a first central processing unit (CPU) node to generate time stamp counter (TSC) values based on a first clock signal and a second CPU node to generate TSC values based on a second clock signal. In some examples, the first CPU node is to determine at least one network timer time stamp based on the TSC values based on the first clock signal and the second CPU node is to determine at least one network timer time stamp based on the TSC values based on the second clock signal. In some examples, determine at least one network timer time stamp based on the TSC values based on the first clock signal is based on (i) a relationship between the first clock signal and a network interface device main timer and (ii) a relationship between a network timer source and the network interface device main timer.

公开(公告)号：US12177003B2

公开(公告)日：2024-12-24

申请号：US17205869

申请日：2021-03-18

Applicant: Intel Corporation

Inventor： Mark Bordogna ,  Srinivasan S. Iyengar

IPC: H04J3/06 ,  H04L43/106 ,  H04L69/28

Abstract: Methods and apparatus for data plane control of network time sync protocol in multi-host systems. A network interface controller (NIC) is configured to implement a network data plane that is associated with a software-based control plane implemented in the multi-host system. The NIC includes a primary timer and secondary timers at distributed endpoints such as network ports. The NIC receives network time packets having network timestamps and employs a secondary timer to associate a local timestamp with the packets. The network and local timestamps are compared by a network intellectual property block (network IP) in the data plane datapath to adjust the primary and secondary timer(s) to match the network time. The network IP uses a 2-bit wire protocol to increment and/or decrement the primary and secondary timer(s) that enables the timers to be adjusted with a nanosecond granularity.