公开(公告)号：US10797858B2

公开(公告)日：2020-10-06

申请号：US15887290

申请日：2018-02-02

Applicant: Intel Corporation

Inventor： Vikram B Suresh ,  Sanu K. Mathew ,  Sudhir K Satpathy ,  Vinodh Gopal

IPC: H04L9/00 ,  H04L9/06 ,  G09C1/00 ,  G06F17/16

Abstract: Modifications to Advanced Encryption Standard (AES) hardware acceleration circuitry are described to allow hardware acceleration of the key operations of any non-AES block cipher, such as SMT and Camellia. In some embodiments the GF(28) inverse computation circuit in the AES S-box is used to compute X−1 (where X is the input plaintext or ciphertext byte), and hardware support is added to compute parallel GF(28) matrix multiplications. The embodiments described herein have minimal hardware overhead while achieving greater speed than software implementations.

公开(公告)号：US10395035B2

公开(公告)日：2019-08-27

申请号：US15277195

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Sanu K. Mathew ,  Sudhir K Satpathy ,  Vikram B Suresh ,  Patrick Koeberl

IPC: H01L27/02 ,  G06F21/56 ,  G06F21/72 ,  G06F21/75 ,  H01L23/00

Abstract: Some embodiments include apparatuses having diffusion regions located adjacent each other in a substrate, and connections coupled to the diffusion regions. The diffusion regions include first diffusion regions, second diffusion regions, and third diffusion regions. One of the second diffusion regions and one of the third diffusion regions are between two of the first diffusion regions. One of the first diffusion regions and one of the third diffusion regions are between two of the second diffusion regions. The connections include a first connection coupled to each of the first diffusion regions, a second connection coupled to each of the second diffusion regions, and a third connection coupled to each of the third diffusion regions.