公开(公告)号：US12081649B2

公开(公告)日：2024-09-03

申请号：US17010577

申请日：2020-09-02

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  Kirk Yap

IPC: G06F21/64 ,  G06F11/07 ,  G06F11/10 ,  H04L9/06 ,  H04L9/32

CPC classification number: H04L9/0643 ,  G06F11/0772 ,  G06F11/1004 ,  G06F11/1044 ,  H04L9/0637 ,  H04L9/3242

Abstract: An apparatus of an aspect includes an encryption unit to receive unencrypted data. The encryption unit is to encrypt the unencrypted data to generate encrypted data. The apparatus also includes circuitry coupled with the encryption unit. The circuitry is to generate a first checksum for a copy of the unencrypted data, generate a second checksum for a copy of the encrypted data, and combine the first and second checksums to generate a first value.

公开(公告)号：US12074618B2

公开(公告)日：2024-08-27

申请号：US17128787

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： James Guilford ,  Vinodh Gopal ,  Daniel Cutter

IPC: H03M7/42 ,  G06F9/46 ,  H03M7/30

CPC classification number: H03M7/42 ,  G06F9/461 ,  H03M7/3086

Abstract: An embodiment of an integrated circuit may comprise a hardware compressor to compress data, the hardware compressor including circuitry to store input data in a history buffer, compute one or more code tables based on the input data, and compute a compression stream header based on the computed one or more code tables. Other embodiments are disclosed and claimed.

公开(公告)号：US20240020428A1

公开(公告)日：2024-01-18

申请号：US18476026

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Akhilesh Thyagaturu ,  Jason Howard ,  Nicholas Ross ,  Sanjaya Tayal ,  Vinodh Gopal

IPC: G06F21/85 ,  G06F21/71 ,  G06F21/57

CPC classification number: G06F21/85 ,  G06F21/71 ,  G06F21/577 ,  G06F2221/034

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to generate and manage a firewall policy. An example includes interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to determine whether an operation is allowed to pass between a first component on a system-on-chip (SoC) and a second component on the SoC, detect an interconnect between the first component on the SoC and the second component on the SoC, cause the interconnect to filter the operation based on the determination of whether the operation is allowed to pass between the first component and the second component, and transmit a request to filter the operation based on the determination of whether the operation is allowed to pass between the first component and the second component.

公开(公告)号：US20230297371A1

公开(公告)日：2023-09-21

申请号：US17695554

申请日：2022-03-15

Applicant: Intel Corporation

Inventor： Fabian Boemer ,  Vinodh Gopal

IPC: G06F9/30 ,  G06F7/57

CPC classification number: G06F9/3001 ,  G06F7/57 ,  G06F9/3016

Abstract: An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include respective fields for one or more source operands, one or more destination operands, and an opcode, the opcode to indicate execution circuitry is to perform a fused multiple multiplication and addition-subtraction operation, and execution circuitry to execute the decoded instruction according to the opcode to retrieve data from one or more locations indicated by the one or more source operands, to perform the fused multiple multiplication and addition-subtraction indicated by the opcode on four or more arguments indicated by the retrieved data to produce one or more results. Other embodiments are disclosed and claimed.

公开(公告)号：US20230247486A1

公开(公告)日：2023-08-03

申请号：US18130695

申请日：2023-04-04

Applicant: Intel Corporation

Inventor： Akhilesh Thyagaturu ,  Saidulu Aldas ,  Mohit Kumar Garg ,  Vinodh Gopal ,  Serey Kong

IPC: H04W28/10 ,  H04W76/36 ,  H04W28/06

CPC classification number: H04W28/10 ,  H04W28/06 ,  H04W76/36

Abstract: Dynamic resource reconfiguration based on workload semantics and behavior. A controller may receive, from a core network, a request for an end-to-end managed connection, the end-to-end managed connection for an application executing on a server and an application executing on a client device, where the client device is coupled to the controller via a radio access network (RAN). The controller may determine a policy for the end-to-end managed connection. The controller may apply one or more parameters of the policy to the end-to-end managed connection.

公开(公告)号：US20230140257A1

公开(公告)日：2023-05-04

申请号：US17514523

申请日：2021-10-29

Applicant: Intel Corporation

Inventor： Fabian Boemer ,  Vinodh Gopal ,  Gelila Seifu ,  Sejun Kim ,  Jack Crawford

IPC: G06F9/30

Abstract: One embodiment provides a processor comprising first circuitry to decode an instruction into a decoded instruction, the instruction to indicate a first source operand, a second source operand and a third operand, and second circuitry including a processing resource to execute the decoded instruction. Responsive to the decoded instruction, the processing resource is to output a result of a modular addition operation based on a data element of first source operand data plus a data element of second source operand data modulo a data element of third operand data, provided that the data elements of the first operand data and second operand data are less than the data element of the third operand data.

公开(公告)号：US20230081763A1

公开(公告)日：2023-03-16

申请号：US17476726

申请日：2021-09-16

Applicant: Intel Corporation

Inventor： Fabian Boemer ,  Vinodh Gopal ,  Gelila Seifu ,  Sejun Kim ,  Jack Crawford

IPC: G06F9/30 ,  G06F7/72 ,  G06F7/49

Abstract: One embodiment provides a processor comprising first circuitry to decode an instruction into a decoded instruction, the instruction to indicate a first source operand and a second source operand and second circuitry including a processing resource to execute the decoded instruction, wherein responsive to the decoded instruction, the processing resource is to output a result of first source operand data minus second source operand data in response to a determination by the processing resource that the first source operand data is greater than or equal to the second source operand data, otherwise the processing resource is to output the first source operand data.

公开(公告)号：US11531542B2

公开(公告)日：2022-12-20

申请号：US17393361

申请日：2021-08-03

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Matthew C. Merten ,  Tong Li ,  Bret L. Toll

IPC: G06F9/30 ,  G06F9/38

Abstract: A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

公开(公告)号：US20220197643A1

公开(公告)日：2022-06-23

申请号：US17133618

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Adarsh Chauhan ,  Vinodh Gopal ,  Vedvyas Shanbhogue ,  Sreenivas Subramoney ,  Wajdi Feghali

IPC: G06F9/30 ,  G06F12/0875

Abstract: Methods and apparatus relating to speculative decompression within processor core caches are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into a plurality of cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the plurality of cachelines of the cache of the processor core in response to the second micro operation. The decompression instruction causes the DE circuitry to perform an out-of-order decompression of the plurality of cachelines. Other embodiments are also disclosed and claimed.

公开(公告)号：US10996936B2

公开(公告)日：2021-05-04

申请号：US15634464

申请日：2017-06-27

Applicant: INTEL CORPORATION

Inventor： Vinodh Gopal

IPC: G06F9/44 ,  G06F9/30 ,  G06F9/46 ,  G06F16/901 ,  G06F9/455 ,  H04L29/08 ,  G06F8/51 ,  G06F8/41 ,  H04L29/06

Abstract: Techniques and apparatus for distributing code via a translation process are described. In one embodiment, for example, an apparatus may include at least one memory and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a source code element to be translated to a target code element, determine source code information for the source code element, provide a translation request corresponding to the source code to a translation service, receive the target code element from the translation service, and execute the target code element in place of the source code element. Other embodiments are described and claimed.