公开(公告)号：US20230205527A1

公开(公告)日：2023-06-29

申请号：US17560547

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Wing Shek WONG ,  Jonathan COMBS ,  Mark CHARNEY

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30098 ,  G06F9/30025

Abstract: Techniques for data type conversion using an instruction are described. An exemplary instruction includes fields for an opcode, an identification of source operands, and an identification of destination operand, wherein the opcode is to indicate execution circuitry and/or memory access circuitry is to convert 32-bit floating point values from the identified source operands into 16-bit floating point values and store 16-bit floating point values in data element positions of the identified destination operand.

公开(公告)号：US20230205521A1

公开(公告)日：2023-06-29

申请号：US17560534

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Wing Shek WONG ,  Jonathan COMBS ,  Mark CHARNEY

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30025 ,  G06F9/3818 ,  G06F9/30112

Abstract: Techniques for data type conversion are described. An example uses an instruction that is to include fields for an opcode, an identification of source operand location, and an identification of destination operand location, wherein the opcode is to indicate instruction processing circuitry is to convert a 16-bit floating-point value from the identified source operand location into a 32-bit floating point value and store that 32-bit floating point value in one or more data element positions of the identified destination operand.

公开(公告)号：US20230205522A1

公开(公告)日：2023-06-29

申请号：US17560557

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Wing Shek WONG ,  Jonathan COMBS ,  Mark CHARNEY

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30025 ,  G06F9/3818 ,  G06F9/30112

Abstract: Techniques for data type conversion via instruction are described. An exemplary instruction is to include fields for an opcode, an identification of a source operand, and an identification of destination operand, wherein the opcode is to indicate instruction processing circuitry is to convert odd 16-bit floating point values from the identified source operand into 32-bit floating point values and store the 32-bit floating point values in data element positions of the identified destination operand.

公开(公告)号：US20250004764A1

公开(公告)日：2025-01-02

申请号：US18217544

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Michael ESPIG ,  Menachem ADELMAN ,  Jonathan COMBS ,  Amit GRADSTEIN ,  Christopher J. HUGHES ,  Vivekananthan SANJEEPAN ,  Wing Shek WONG

IPC: G06F9/30

Abstract: Techniques for providing 512-bit operands or smaller are described. In some examples, a prefix of an instruction is utilized to define the operand (vector) length. For example, an instruction is to at least include fields for a prefix, an opcode, and operand addressing information, wherein the prefix and addressing information are to be used by decoder circuitry to determine support for a particular a vector length for one or more operands of the instance of the single instruction and the opcode is to indicate one or more operations to perform on the one or more operands.