公开(公告)号：US20230205521A1

公开(公告)日：2023-06-29

申请号：US17560534

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Wing Shek WONG ,  Jonathan COMBS ,  Mark CHARNEY

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30025 ,  G06F9/3818 ,  G06F9/30112

Abstract: Techniques for data type conversion are described. An example uses an instruction that is to include fields for an opcode, an identification of source operand location, and an identification of destination operand location, wherein the opcode is to indicate instruction processing circuitry is to convert a 16-bit floating-point value from the identified source operand location into a 32-bit floating point value and store that 32-bit floating point value in one or more data element positions of the identified destination operand.

公开(公告)号：US20250028532A1

公开(公告)日：2025-01-23

申请号：US18375488

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Jason AGRON ,  Andreas KLEEN ,  Ching-Tsun CHOU ,  Jonathan COMBS ,  Hongjiu LU ,  Jared Warner STARK, IV ,  Jeff WIEDEMEIER

IPC: G06F9/30

Abstract: Techniques for performing an unconditional jump are described. In some examples, an instruction is processed to perform the unconditional jump. In some examples, the instruction is to at least include one or more fields for an opcode and a 64-bit bit immediate, wherein the 64-bit immediate is to encode an absolute address and the opcode is to indicate execution circuitry is jump to the absolute address.

公开(公告)号：US20250004764A1

公开(公告)日：2025-01-02

申请号：US18217544

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Michael ESPIG ,  Menachem ADELMAN ,  Jonathan COMBS ,  Amit GRADSTEIN ,  Christopher J. HUGHES ,  Vivekananthan SANJEEPAN ,  Wing Shek WONG

IPC: G06F9/30

Abstract: Techniques for providing 512-bit operands or smaller are described. In some examples, a prefix of an instruction is utilized to define the operand (vector) length. For example, an instruction is to at least include fields for a prefix, an opcode, and operand addressing information, wherein the prefix and addressing information are to be used by decoder circuitry to determine support for a particular a vector length for one or more operands of the instance of the single instruction and the opcode is to indicate one or more operations to perform on the one or more operands.

公开(公告)号：US20230205527A1

公开(公告)日：2023-06-29

申请号：US17560547

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Wing Shek WONG ,  Jonathan COMBS ,  Mark CHARNEY

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30098 ,  G06F9/30025

Abstract: Techniques for data type conversion using an instruction are described. An exemplary instruction includes fields for an opcode, an identification of source operands, and an identification of destination operand, wherein the opcode is to indicate execution circuitry and/or memory access circuitry is to convert 32-bit floating point values from the identified source operands into 16-bit floating point values and store 16-bit floating point values in data element positions of the identified destination operand.

公开(公告)号：US20220100500A1

公开(公告)日：2022-03-31

申请号：US17033649

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Thomas MADAELIL ,  Jonathan COMBS ,  Vikash AGARWAL

IPC: G06F9/22 ,  G06F9/38

Abstract: Systems, methods, and apparatuses relating to circuitry to implement out-of-order access to a shared microcode sequencer by a clustered decode pipeline are described. In one embodiment, a hardware processor core includes a first decode cluster comprising a plurality of decoder circuits, a second decode cluster comprising a plurality of decoder circuits, a fetch circuit to fetch a first block of instructions and send the first block of instructions to the first decode cluster for decoding, and fetch a second block of instructions younger in program order than the first block of instructions and send the second block of instructions to the second decode cluster for decoding, a microcode sequencer comprising a memory that stores a plurality of micro-operations, and an arbitration circuit to arbitrate access by the first decode cluster and the second decode cluster to a shared read port of the memory, wherein the arbitration circuit is to allow the second decode cluster decoding the second block of instructions access to the shared read port of the memory instead of the first decode cluster decoding the first block of instructions when an instruction of the second block of instructions has a number of corresponding micro-operations in the microcode sequencer below an arbitration threshold.

公开(公告)号：US20230205522A1

公开(公告)日：2023-06-29

申请号：US17560557

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Wing Shek WONG ,  Jonathan COMBS ,  Mark CHARNEY

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30025 ,  G06F9/3818 ,  G06F9/30112

Abstract: Techniques for data type conversion via instruction are described. An exemplary instruction is to include fields for an opcode, an identification of a source operand, and an identification of destination operand, wherein the opcode is to indicate instruction processing circuitry is to convert odd 16-bit floating point values from the identified source operand into 32-bit floating point values and store the 32-bit floating point values in data element positions of the identified destination operand.

公开(公告)号：US20220100516A1

公开(公告)日：2022-03-31

申请号：US17033680

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Thomas MADAELIL ,  Jonathan COMBS ,  Khary ALEXANDER ,  Martin LICHT ,  Vikash AGARWAL

IPC: G06F9/30 ,  G06F12/0875

Abstract: Systems, methods, and apparatuses for power efficient generation of length markers for a variable length instruction set are described. In one embodiment, a hardware processor core includes a decoder circuit to decode instructions into decoded instructions, an execution circuit to execute the decoded instructions, an instruction cache, an instruction length decoder circuit, a predecode cache comprising a predecode bit, for each section of multiple sections of instruction data, that indicates when that section is identified as an end boundary of a variable length instruction, an incomplete decode table comprising a bit, for each proper subset of sections of instruction data, that indicates when that proper subset of sections has one or more invalid predecode bits in the predecode cache; and a fetch circuit to, for an incoming address of instruction data, perform a lookup in the instruction cache and the incomplete decode table, and, when there is a hit in the instruction cache for the instruction data at the incoming address and a hit in the incomplete decode table that indicates a proper subset of sections of the instruction data for the incoming address has one or more invalid predecode bits in the predecode cache, causes the instruction length decoder circuit to generate one or more predecode bits for the proper subset of sections of the instruction data for the incoming address that has the one or more invalid predecode bits.