公开(公告)号：US20210383049A1

公开(公告)日：2021-12-09

申请号：US17406534

申请日：2021-08-19

Applicant: Intel Corporation

Inventor： Ning Cheng ,  Xiangyong Wang ,  Mahesh A. Iyer

IPC: G06F30/392 ,  G06F30/34 ,  G06F30/394 ,  G06F30/398

Abstract: An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.

公开(公告)号：US20190095571A1

公开(公告)日：2019-03-28

申请号：US15718685

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Ning Cheng ,  Xiangyong Wang ,  Mahesh A. Iyer

IPC: G06F17/50

Abstract: An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.

公开(公告)号：US20240028815A1

公开(公告)日：2024-01-25

申请号：US18375299

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Xiangyong Wang ,  David Kehlet ,  Diana Cristina Ojeda Aristizabal ,  Ian Kuon ,  Mehmet Avci

IPC: G06F30/398

CPC classification number: G06F30/398 ,  G06F2119/12

Abstract: Integrated circuit devices, methods, and circuitry are provided for performing timing analysis for chip-to-chip connections between integrated circuits in a multichip package. A system may include an integrated circuit package and a computing system. The integrated circuit package may have a first integrated circuit connected to a second integrated circuit via a chip-to-chip connection. The chip-to-chip connection may also be connected to a package ball. The computing system may perform timing analysis on a circuit design for the first integrated circuit with respect the chip-to-chip connection based on user-specified parasitic data relating to the connection to the package ball.

公开(公告)号：US11113442B2

公开(公告)日：2021-09-07

申请号：US15718685

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Ning Cheng ,  Xiangyong Wang ,  Mahesh A. Iyer

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/34 ,  G06F30/394 ,  G06F30/398 ,  G06F119/04

Abstract: An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.