公开(公告)号：US20240037036A1

公开(公告)日：2024-02-01

申请号：US17876081

申请日：2022-07-28

Applicant: Intel Corporation

Inventor： Mark Dechene ,  Ryan Carlson ,  Ricardo Daniel Queiros Alves ,  Yan Zeng ,  Richard Klass ,  Brendan West

IPC: G06F12/0815 ,  G06F12/0864

CPC classification number: G06F12/0815 ,  G06F12/0864 ,  G06F2212/1021

Abstract: Techniques for scheduling merged store operations are described. In an embodiment, an apparatus includes a data cache; a fill buffer; a store buffer to store first information associated with a first retired store operation and second information associated with a second retired store operation; a store coalescing buffer (SCB) to receive the first information from the store buffer, to store the first information in an SCB entry, to merge the second information from the store buffer into the entry, and to provide data associated with the entry for a write to the data cache or the fill buffer; and a global store scheduler (GSS) to schedule the write relative to an other write from an other SCB in compliance with one or more store ordering rules.