公开(公告)号：US20240126702A1

公开(公告)日：2024-04-18

申请号：US17949803

申请日：2022-09-21

Applicant: Intel Corporation

Inventor： Mark Dechene ,  Ryan Carlson ,  Sudeepto Majumdar ,  Rafael Trapani Possignolo ,  Paula Petrica ,  Richard Klass ,  Meenakshi Marathe

IPC: G06F12/1027 ,  G06F12/0882

CPC classification number: G06F12/1027 ,  G06F12/0882 ,  G06F2212/1021

Abstract: Techniques for slicing memory of a hardware processor core by linear address are described. In certain examples, a hardware processor core includes memory circuitry having: a cache comprising a plurality of slices of memory, wherein each of a plurality of cache lines of memory are only stored in a single slice, and each slice stores a different range of address values compared to any other slice, wherein each of the plurality of slices of memory comprises: an incomplete load buffer to store a load address from the address generation circuit for a load request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the load address being within a range of address values of that memory slice, a store address buffer to store a store address from the address generation circuit for a store request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the store address being within a range of address values of that memory slice, a store data buffer to store data, including the data for the store request operation that is to be stored at the store address, for each store request operation broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, and a store completion buffer to store the data for the store request operation in response to the store address being stored in the store address buffer of that memory slice, and, in response, clear the store address for the store request operation from the store address buffer and clear the data for the store request operation from the store data buffer.

公开(公告)号：US20240037036A1

公开(公告)日：2024-02-01

申请号：US17876081

申请日：2022-07-28

Applicant: Intel Corporation

Inventor： Mark Dechene ,  Ryan Carlson ,  Ricardo Daniel Queiros Alves ,  Yan Zeng ,  Richard Klass ,  Brendan West

IPC: G06F12/0815 ,  G06F12/0864

CPC classification number: G06F12/0815 ,  G06F12/0864 ,  G06F2212/1021

Abstract: Techniques for scheduling merged store operations are described. In an embodiment, an apparatus includes a data cache; a fill buffer; a store buffer to store first information associated with a first retired store operation and second information associated with a second retired store operation; a store coalescing buffer (SCB) to receive the first information from the store buffer, to store the first information in an SCB entry, to merge the second information from the store buffer into the entry, and to provide data associated with the entry for a write to the data cache or the fill buffer; and a global store scheduler (GSS) to schedule the write relative to an other write from an other SCB in compliance with one or more store ordering rules.