公开(公告)号：US11870449B2

公开(公告)日：2024-01-09

申请号：US17638739

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Elan Banin ,  Yaniv Cohen ,  Ofir Degani ,  Igal Kushnir

IPC: H03L7/099 ,  G06F1/08 ,  H03L7/093

CPC classification number: H03L7/0992 ,  G06F1/08 ,  H03L7/093

Abstract: A clock generator calibration system can include a phased-locked loop and a correction circuit. The PLL can generate an output clock signal, and the correction circuit can adjust a frequency signal of the PLL based on a digital signal of the PLL. The digital signal can be generated based on the adjusted frequency signal.

公开(公告)号：US20220393690A1

公开(公告)日：2022-12-08

申请号：US17638739

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Elan Banin ,  Yaniv Cohen ,  Ofir Degani ,  Igal Kushnir

IPC: H03L7/099 ,  H03L7/093 ,  G06F1/08

Abstract: A clock generator calibration system can include a phased-locked loop and a correction circuit. The PLL can generate an output clock signal, and the correction circuit can adjust a frequency signal of the PLL based on a digital signal of the PLL. The digital signal can be generated based on the adjusted frequency signal.