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    Apparatus and method for transmitting a bit in addition to a plurality of payload data symbols of a communication protocol, and apparatus and method for decoding a data signal
    2.
    发明授权
    Apparatus and method for transmitting a bit in addition to a plurality of payload data symbols of a communication protocol, and apparatus and method for decoding a data signal 有权

    公开(公告)号：US11902062B2

    公开(公告)日：2024-02-13

    申请号：US17754311

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Elan Banin ,  Rotem Banin ,  Ofir Degani ,  Eytan Mann

    IPC: H03K9/08 ,  H04L25/49

    CPC classification number: H04L25/4902

    Abstract: An apparatus for transmitting a bit in addition to a plurality of payload data symbols of a communication protocol is provided. The apparatus comprises an input interface configured to receive information about a bit value of the bit. Further, the apparatus comprises a transmission circuit configured to, if the bit value is a first value, transmit the plurality of payload data symbols at predetermined positions in a data signal as pulses of variable pulse length. The respective pulse length of each of the pulses is selected based on the symbol value of the payload data symbol represented by the respective pulse. If the bit value is a second value, the transmission circuit is configured to transmit a pulse exhibiting a pulse length being longer than a maximum payload data symbol pulse length defined in the communication protocol at the predetermined position of the pulse for the d-th payload data symbol of the plurality of payload data symbols, d=k+i if k+i≤z. d=([k+i] mod z) if k+i>z. k is the symbol value of the i-th payload data symbol of the plurality of payload data symbols, z is the number of possible symbol values of the payload data symbols defined in the communication protocol, and 1≤i≤z.

    EMPLOYING DITHERED CLOCK IN DISTRIBUTED RADIO SYSTEM
    3.
    发明公开
    EMPLOYING DITHERED CLOCK IN DISTRIBUTED RADIO SYSTEM 审中-公开

    公开(公告)号：US20230413195A1

    公开(公告)日：2023-12-21

    申请号：US17841907

    申请日：2022-06-16

    Applicant: Intel Corporation

    Inventor： Evgeny Shumaker ,  Elan Banin ,  Ofir Degani

    IPC: H04W56/00

    CPC classification number: H04W56/001

    Abstract: A radio-head apparatus can comprise memory to store dithering information of the apparatus. The radio-head can further include radio-head circuitry to generate a clock signal according to the dithering information and to provide a wakeup signal, subsequent to commencement of clock signal generation, to instruct a secondary RH to use the clock signal of the RH. The same wakeup signal is also used to synchronize the finite state machines of both RHs that govern and report the dithering information. Synchronization of the FSM allows estimation of information to be used in the secondary RH for compensation of the clock dithering applied in the primary RH. Other systems and apparatuses are described.

    Methods and arrangements for direct current estimation of a wireless communication packet
    7.
    发明授权
    Methods and arrangements for direct current estimation of a wireless communication packet 有权
    无线通信分组的直流估计的方法和布置

    公开(公告)号：US09374197B2

    公开(公告)日：2016-06-21

    申请号：US14229803

    申请日：2014-03-28

    Applicant: Intel Corporation

    Inventor： Moshe Teplitsky ,  Michael Genossar ,  Elan Banin

    IPC: H04L1/00 ,  H04B1/30

    CPC classification number: H04L1/0045 ,  H04B1/30 ,  H04B2001/305 ,  H04W56/0035

    Abstract: Logic for direct current (DC) estimation of a wireless communication packet. Logic may determine a first DC estimation based upon a first set of sequences in a preamble of the wireless communication packet. Logic may determine a second DC estimation based upon a second set of sequences in the preamble. Logic may select one of the DC estimations based upon a frequency-offset estimation. Logic may remove one of the DC estimations from the packet. Logic to null DC bins that result from a Fourier transform of the packet to mitigate transmitter DC bias. And logic to determine a correction for the packet based upon a difference between a predetermined guard interval value and a received guard interval value and to apply the correction to the packet.

    Abstract translation: 用于无线通信分组的直流（DC）估计的逻辑。 逻辑可以基于无线通信分组的前导码中的第一组序列来确定第一DC估计。 逻辑可以基于前导码中的第二组序列来确定第二DC估计。 逻辑可以基于频率偏移估计来选择直流估计之一。 逻辑可以从分组中去除一个DC估计。 逻辑来清除由数据包的傅立叶变换产生的直流信道，以减轻发射机直流偏置。 以及用于基于预定保护间隔值和接收到的保护间隔值之间的差来确定对分组的校正并且将校正应用于分组的逻辑。

    Methods and devices for TDC resolution improvement
    8.
    发明授权
    Methods and devices for TDC resolution improvement 有权

    公开(公告)号：US12191871B2

    公开(公告)日：2025-01-07

    申请号：US17355217

    申请日：2021-06-23

    Applicant: Intel Corporation

    Inventor： Evgeny Shumaker ,  Elan Banin ,  Ofir Degani ,  Gil Horovitz

    IPC: H03L7/24 ,  G04F10/00 ,  H03L7/085 ,  H03L7/099

    Abstract: A TDC circuit configured to receive a reference clock (REF) signal and a signal derived from a LO; generate a plurality of digital values indicative of a measured phase difference between the signal derived from the LO and the REF signal, wherein each of the plurality of digital values are determined from a unique set of a plurality of sets of TDC measurement component quantization levels; generate a combined series of quantization levels based on a combination of the plurality of sets of TDC measurement component quantization levels; and determine a combined digital value from the combined series of quantization levels and at least one of the plurality of digital values to generate an output of the TDC circuit. The combined series of quantization levels may be generated by summing simultaneously occurring levels of each of the plurality of sets of TDC measurement component quantization levels together.

    APPARATUS, SYSTEM AND METHOD OF PHASE SHIFTING
    10.
    发明公开
    APPARATUS, SYSTEM AND METHOD OF PHASE SHIFTING 审中-公开

    公开(公告)号：US20240113696A1

    公开(公告)日：2024-04-04

    申请号：US17958340

    申请日：2022-10-01

    Applicant: INTEL CORPORATION

    Inventor： Elan Banin ,  Rotem Banin ,  Ashoke Ravi ,  Assaf Ben-Bassat ,  Ofir Degani

    IPC: H03H11/16 ,  G06F1/08

    CPC classification number: H03H11/16 ,  G06F1/08 ,  H04L27/2067

    Abstract: For example, a phase shifter may include an input to receive an input clock signal having an input frequency and an input phase. For example, the phase shifter may include a quadrature phase-shift generator configured to generate a first signal and a second signal based on the input clock signal, the first and second signals having the input frequency, wherein a phase of the first signal is based on the input phase, wherein a phase of the second signal is shifted by a quadrature phase-shift relative to the phase of the first signal. For example, the phase shifter may include an output to provide an output based on the first signal and the second signal.

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