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公开(公告)号：US11270999B2
公开(公告)日：2022-03-08
申请号：US17224258
申请日：2021-04-07
IPC分类号： H01L27/108 , G11C11/404 , G11C11/401
摘要： The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.
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公开(公告)号：US11315634B1
公开(公告)日：2022-04-26
申请号：US17074763
申请日：2020-10-20
IPC分类号： G11C13/00
摘要： A device includes at least one tunable resistive element. Each tunable resistive element comprises a first terminal, a second terminal, and a dielectric layer arranged between the first and second terminals. The device is configured to apply at least one electrical set pulse to the resistive elements to form a conductive filament comprising a plurality of oxygen vacancies in the dielectric layer. The device is configured to apply at least one electrical reset pulse to displace a subset of the oxygen vacancies of the conductive filament. The at least one electrical reset pulse comprises a first part, which is adapted to increase the temperature of the conductive filament and increase the mobility of the oxygen vacancies of the conductive filament, and a second part, which is configured to displace the subset of the oxygen vacancies of the conductive filament.
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公开(公告)号：US20210175234A1
公开(公告)日：2021-06-10
申请号：US16703916
申请日：2019-12-05
IPC分类号： H01L27/108 , G11C11/404
摘要： The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.
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公开(公告)号：US11164068B1
公开(公告)日：2021-11-02
申请号：US17097109
申请日：2020-11-13
摘要： An electronic circuit for enabling an efficient use of an oscillating neural network for feature recognition may be provided. The electronic circuit comprises a network of coupled voltage-controlled oscillators, wherein each of the voltage-controlled oscillators is adapted for receiving an edge input signal which is phase-shifted by a fraction of a period length of the voltage-controlled oscillators according to a signal strength of an analog input signal allotted to a respective one of the voltage-controlled oscillators, and an active output circuit. The active output circuit includes input terminals connected to selected ones of the voltage-controlled oscillators, an adder portion for adding input signals present at the input terminals, and a non-linear amplifier, an which input line is of the non-linear amplifier being connected to an output line of the adder portion, thereby an efficient use of an oscillating neural network.
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公开(公告)号：US20210225845A1
公开(公告)日：2021-07-22
申请号：US17224258
申请日：2021-04-07
IPC分类号： H01L27/108 , G11C11/404
摘要： The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.
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公开(公告)号：US11031402B1
公开(公告)日：2021-06-08
申请号：US16703916
申请日：2019-12-05
IPC分类号： H01L27/108 , G11C11/404 , G11C11/401
摘要： The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.
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公开(公告)号：US20220122662A1
公开(公告)日：2022-04-21
申请号：US17074763
申请日：2020-10-20
IPC分类号： G11C13/00
摘要： A device includes at least one tunable resistive element. Each tunable resistive element comprises a first terminal, a second terminal, and a dielectric layer arranged between the first and second terminals. The device is configured to apply at least one electrical set pulse to the resistive elements to form a conductive filament comprising a plurality of oxygen vacancies in the dielectric layer. The device is configured to apply at least one electrical reset pulse to displace a subset of the oxygen vacancies of the conductive filament. The at least one electrical reset pulse comprises a first part, which is adapted to increase the temperature of the conductive filament and increase the mobility of the oxygen vacancies of the conductive filament, and a second part, which is configured to displace the subset of the oxygen vacancies of the conductive filament.
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公开(公告)号：US20220004876A1
公开(公告)日：2022-01-06
申请号：US16919367
申请日：2020-07-02
摘要： The network comprises at least one network layer in which a plurality of electronic oscillators, interconnected via programmable coupling elements storing respective network weights, generate oscillatory signals at time delays dependent on the input signal to propagate the input signal from an input to an output of that layer. The network is adapted to provide a network output signal dependent substantially linearly on phase of oscillatory signals in the last layer of the network. The method includes calculating a network error dependent on the output signal and a desired output for the training sample, and calculating updates for respective network weights by backpropagation of the error such that weight-updates for a network layer are dependent on a vector of time delays at the input to that layer and the calculated error at the output of that layer.
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