公开(公告)号：US20250157890A1

公开(公告)日：2025-05-15

申请号：US18945958

申请日：2024-11-13

Applicant: Japan Display Inc.

Inventor： Takamitsu FUJIMOTO ,  Kenji HARADA ,  Takayuki SUZUKI

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/423

Abstract: A semiconductor device according to an embodiment of the present invention includes: a first semiconductor layer; a first gate electrode facing the first semiconductor layer; a second gate electrode facing the first semiconductor layer and supplied with the same voltage as the first gate electrode; a first gate insulating layer between the first semiconductor layer and the first gate electrode, and between the first semiconductor layer and the second gate electrode; a second semiconductor layer sandwiching the first gate electrode with the first semiconductor layer; a third gate electrode facing the second semiconductor layer on an opposite side to the first gate electrode with respect to the second semiconductor layer, and overlapping the first gate electrode in a plan view; and a second gate insulating layer between the second semiconductor layer and the third gate electrode.

公开(公告)号：US20250022419A1

公开(公告)日：2025-01-16

申请号：US18768362

申请日：2024-07-10

Applicant: Japan Display Inc.

Inventor： Yukio TANAKA ,  Tetsuo MORITA ,  Kenji HARADA

IPC: G09G3/3233 ,  H10K59/12 ,  H10K59/121

Abstract: A display device includes a substrate including a display region; and a first pixel arranged in a first region on an outer edge of the display region, and a second pixel arranged in a second region surrounded by the first region. Each of the first pixel and the second pixel includes a first transistor, a second transistor, a first capacitor, a third transistor, and a seventh transistor. A capacitance of a capacitor connected to the gate electrode of the second transistor of the first pixel is different from a capacitance of a capacitor connected to the gate electrode of the second transistor of the second pixel.

公开(公告)号：US20240331632A1

公开(公告)日：2024-10-03

申请号：US18614807

申请日：2024-03-25

Applicant: Japan Display Inc.

Inventor： Kenji HARADA ,  Hideyuki TAKAHASHI ,  Tetsuo MORITA ,  Masahiro KUBOTA

IPC: G09G3/3233 ,  H10K59/131

CPC classification number: G09G3/3233 ,  H10K59/131 ,  G09G2300/0842 ,  G09G2310/08

Abstract: To effectively inhibit corrosion of a connecting terminal in an EL display, an array substrate includes a plurality of light emitting elements that are regularly arrayed, a scanning circuit that supplies the plurality of light emitting elements with at least a first scanning signal and a second scanning signal, and a plurality of connection terminals that are connected to the scanning circuit by a plurality of connection lines. The plurality of connection terminals include two adjacent connection terminals, an inverting circuit is interposed in at least one of two connection lines that connect the two adjacent connection terminals with the scanning circuit, and a same logic period in which output signals or input signals of the two adjacent connection terminals both have high potential or low potential in one scanning period is longer than a different logic period, in one scanning period.

公开(公告)号：US20240119893A1

公开(公告)日：2024-04-11

申请号：US18480528

申请日：2023-10-04

Applicant: Japan Display Inc.

Inventor： Kenji HARADA ,  Tetsuo MORITA

IPC: G09G3/3225

CPC classification number: G09G3/3225 ,  G09G2300/0861 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0233

Abstract: According to one embodiment, a display device includes a pixel circuit provided in each of a plurality of pixels, a plurality of flip-flop circuits provided in a shift register and a reset element provided in each of the flip-flop circuits, and the reset element is an n-channel type transistor, the pixel circuit includes a light emitting element, a light emitting power supply and a switch element, and the light emitting element is disconnected from the light emitting power supply while the light emitting power supply is rising.

公开(公告)号：US20220352269A1

公开(公告)日：2022-11-03

申请号：US17657955

申请日：2022-04-05

Applicant: Japan Display Inc.

Inventor： Tetsuo MORITA ,  Sho YANAGISAWA ,  Kenji HARADA ,  Hiroshi TABATAKE ,  Hideyuki TAKAHASHI

IPC: H01L27/32 ,  H01L51/52

Abstract: According to one embodiment, a display device comprising a base, a first insulating layer, a first lower electrode, a second lower electrode, a first wiring, a second insulating layer disposed on the first wiring, a first organic layer disposed on the first lower electrode, a second organic layer disposed on the second lower electrode, a first separation wall disposed on the second insulating layer, and an upper wiring disposed continuously on the first organic layer, the second organic layer, and the first separation wall, wherein the upper wiring is electrically connected to the first wiring via a contact hole that penetrates the first separation wall and the second insulating layer.

公开(公告)号：US20220271115A1

公开(公告)日：2022-08-25

申请号：US17668473

申请日：2022-02-10

Applicant: Japan Display Inc.

Inventor： Kenji HARADA

IPC: H01L27/32

Abstract: According to one embodiment, a display device including a first lower electrode, a second lower electrode, a first wiring that is disposed between the first lower electrode and the second lower electrode, a second insulation layer that is disposed on the first wiring, a first organic layer that is disposed on the first lower electrode, a second organic layer that is disposed on the second lower electrode, a first upper electrode that is disposed on the first organic layer, a second upper electrode that is disposed on the second organic layer, and a second wiring that is disposed on the second insulation layer, opposed to the first wiring, and forms a capacitance between the first wiring and the second wiring.

公开(公告)号：US20240324319A1

公开(公告)日：2024-09-26

申请号：US18734053

申请日：2024-06-05

Applicant: Japan Display Inc.

Inventor： Kenji HARADA

IPC: H10K59/122 ,  H10K50/822

CPC classification number: H10K59/122 ,  H10K50/822

Abstract: According to one embodiment, a display device includes a base, a first insulating layer, first and second lower electrodes, a second insulating layer including a first opening, a second opening, and a first trench, an organic layer including a light-emitting layer and an upper electrode, and the first trench includes a bottom surface and first and second side surfaces, an interval between the first side surface and the second side surface in an upper portion of the first trench is smaller than that in the bottom surface, and the organic layer includes a first portion covering the first lower electrode, a second portion covering the second lower electrode and a third portion disposed on the bottom surface.

公开(公告)号：US20220231100A1

公开(公告)日：2022-07-21

申请号：US17578536

申请日：2022-01-19

Applicant: Japan Display Inc.

Inventor： Kenji HARADA

IPC: H01L27/32 ,  H01L51/52

Abstract: According to one embodiment, a display device includes a base, a first insulating layer, first and second lower electrodes, a second insulating layer including a first opening, a second opening, and a first trench, an organic layer including a light-emitting layer and an upper electrode, and the first trench includes a bottom surface and first and second side surfaces, an interval between the first side surface and the second side surface in an upper portion of the first trench is smaller than that in the bottom surface, and the organic layer includes a first portion covering the first lower electrode, a second portion covering the second lower electrode and a third portion disposed on the bottom surface.

公开(公告)号：US20250160188A1

公开(公告)日：2025-05-15

申请号：US19006498

申请日：2024-12-31

Applicant: Japan Display Inc.

Inventor： Sho YANAGISAWA ,  Tetsuo MORITA ,  Kenji HARADA ,  Hiroshi TABATAKE ,  Hideyuki TAKAHASHI

IPC: H10K59/88 ,  H10K59/122 ,  H10K59/131

Abstract: According to one embodiment, a display device includes a substrate, first and second insulating layers, first and second pixel electrodes, first and second organic layers, first and second feed lines, first and second partitions, and a common electrode including first and second parts covering the first and second organic layers. The first organic layer is between the partitions. The second feed line and the second partition are located between the organic layers. The partitions are shaped such that a width of an upper part is greater than a width of a lower part. The first part is in contact with the first feed line between the first partition and the first organic layer.

公开(公告)号：US20240112617A1

公开(公告)日：2024-04-04

申请号：US18477555

申请日：2023-09-29

Applicant: Japan Display Inc.

Inventor： Kenji HARADA

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G2300/0426 ,  G09G2310/0267

Abstract: According to one embodiment, a CMOS circuit includes a p-channel type transistor including a polycrystalline silicon layer and an n-channel type transistor including an oxide semiconductor layer, and the p-channel transistor and the n-channel transistor are complementarily connected to each other, and the polycrystalline silicon layer and the oxide semiconductor layer overlap each other in plan view.