公开(公告)号：US20240365607A1

公开(公告)日：2024-10-31

申请号：US18626030

申请日：2024-04-03

Applicant: Samsung Display Co., LTD.

Inventor： JUNHYUN PARK ,  HYEONGSEOK KIM ,  HEEJEAN PARK ,  SUNHWA LEE

IPC: H10K59/126 ,  G09G3/3233

CPC classification number: H10K59/126 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2310/08 ,  G09G2320/0233

Abstract: A display device includes: a display panel including a light emitting element and a pixel circuit unit connected to the light emitting element. The pixel circuit unit includes: a first transistor connected between a drive voltage line and the light emitting element and which operates depending on a potential of a first node; a second transistor connected between a data line and a second node; a first capacitor electrode connected to the first node; a second capacitor electrode connected to the second node and which faces the first capacitor electrode; a third capacitor electrode connected to the second node; a fourth capacitor electrode, which faces the third capacitor electrode and is connected to the drive voltage line; a bridge electrode, which connects the second capacitor electrode and the third capacitor electrode; and a shielding electrode, which overlaps the bridge electrode in a plan view.

公开(公告)号：US20240363079A1

公开(公告)日：2024-10-31

申请号：US18028830

申请日：2022-04-22

Applicant: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhengkun Li ,  De Li ,  Haigang Qing ,  Yue Long ,  Cong Liu ,  Qiwei Wang ,  Binyan Wang ,  Zhongliu Yang ,  Tianyi Cheng ,  Ni Yang ,  Qiyang Wu

IPC: G09G3/3275 ,  G09G3/32

CPC classification number: G09G3/3275 ,  G09G3/32 ,  G09G2300/0426 ,  G09G2310/0275 ,  G09G2310/08 ,  G09G2320/0233

Abstract: Provided are a display substrate and a display device. The display substrate includes a base substrate, and a driving circuit layer and a light-emitting device layer on the base substrate. The display substrate includes a light-transmitting display area and a normal display area, the normal display area surrounds at least a portion of the light-transmitting display area. The normal display area includes multiple normal driving circuits and multiple dummy driving circuits; some dummy driving circuit are used for driving light-emitting devices located in the light-transmitting display area. The display substrate further includes multiple normal data lines coupled to the normal driving circuits; at least one normal data line is coupled to a data signal input terminal through a data lead; an orthographic projection of the data lead onto the base substrate at least partially overlaps an orthographic projection of the dummy driving circuit onto the base substrate.

公开(公告)号：US20240363077A1

公开(公告)日：2024-10-31

申请号：US18247464

申请日：2022-06-23

Applicant: HEFEI BOE JOINT TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xuehuan FENG ,  Yongqian LI

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/045

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, and a gate driving circuit and a plurality of signal lines arranged on the base substrate; the plurality of signal lines include a first clock sub-signal line and a second clock sub-signal line; an orthographic projection of the first clock sub-signal line on the base substrate and an orthographic projection of the second clock sub-signal line on the base substrate are arranged side by side, and the first clock sub-signal provided by the first clock sub-signal line is the same as the second clock sub-signal provided by the second clock sub-signal line.

公开(公告)号：US20240363065A1

公开(公告)日：2024-10-31

申请号：US18028743

申请日：2022-05-19

Applicant: MIANYANG BOE OPTOELECTRONICS TECHNOLOGY CO.,Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Yuan SHEN ,  Lin XIONG ,  Jie TU ,  Zifeng WANG ,  Danfeng WANG ,  Jianmin FAN ,  Qing TANG

IPC: G09G3/3233 ,  H10K59/131

CPC classification number: G09G3/3233 ,  H10K59/131 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2320/0247

Abstract: A pixel circuit comprises a drive sub-circuit (101), writing sub-circuit (102), reset sub-circuit (103), voltage stabilizing sub-circuit (104), storage sub-circuit (105) and light emitting element. The drive sub-circuit is configured to provide a driving current to the light emitting element under control of signals of a first node (N1) and a second node (N2); the writing sub-circuit is configured to write a signal from a data signal terminal (Data) to N2 under control of signal of a scan signal terminal (Gate); the storage sub-circuit is configured to store a voltage of N1; the voltage stabilizing sub-circuit is configured to stabilize a voltage of an anode terminal of light emitting element through signal of a voltage stabilizing signal terminal (V1); the reset sub-circuit is configured to reset anode terminal of light emitting element under control of signal of Gate and reset N1 under control of signal of a reset control signal terminal (Reset).

公开(公告)号：US20240363057A1

公开(公告)日：2024-10-31

申请号：US18757470

申请日：2024-06-27

Applicant: Tianma Advanced Display Technology Institute (Xiamen) Co., Ltd.

Inventor： Yingteng ZHAI

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2320/0247

Abstract: A pixel circuit, a display panel, and a display apparatus are provided. The pixel circuit includes a first driving circuit, a second driving circuit, and a first capacitor. The first capacitor includes a first plate electrically connected to an output terminal of the first driving circuit and a second plate electrically connected to the second driving circuit. The first driving circuit is configured to generate a control current based on a first data signal, and the second driving circuit is configured to generate a driving current based on a second data signal and control a flowing period of the driving current based on the control current. A light-emitting element is electrically connected to the second driving circuit to receive the driving current.

公开(公告)号：US12131704B2

公开(公告)日：2024-10-29

申请号：US17643042

申请日：2021-12-07

Applicant: LX Semicon Co., Ltd.

Inventor： Young Bok Kim ,  Won Kim ,  Taiming Piao

IPC: G09G3/3266 ,  G09G3/3208 ,  G09G3/3275

CPC classification number: G09G3/3266 ,  G09G2310/0251 ,  G09G2310/08 ,  G09G2320/043

Abstract: The present disclosure discloses a precharge circuit capable of compensating for a resistance deviation between channels so that sense lines of a display panel can be uniformly charged and a source driver including the same. The precharge circuit may include a voltage terminal configured to provide a reference voltage, a common line connected to the voltage terminal, and channel lines connected to the common line and configured to transfer, to respective sense lines of a display panel, the reference voltage transferred through the common line.

公开(公告)号：US12131703B2

公开(公告)日：2024-10-29

申请号：US17641095

申请日：2019-11-26

Applicant: Samsung Display Co., LTD.

Inventor： Jun Hyun Park ,  Dong Woo Kim ,  An Su Lee ,  Kang Moon Jo

IPC: G09G3/3266 ,  G09G3/3233 ,  G09G3/3291

CPC classification number: G09G3/3266 ,  G09G3/3291 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0223

Abstract: A scan signal driving unit capable of reducing the RC delay of scan control lines in an ultra-high resolution display, such as 8K UHD. The scan signal driving unit includes a plurality of stages configured to sequentially output scan signals, first clock lines to which first clock signals are applied, and second clock lines to which second clock signals are applied. Each of the first clock lines includes a (1-1)-th metal pattern and a (1-2)-th metal pattern disposed on the (1-1)-th metal pattern. Each of the second clock lines includes a (2-1)-th metal pattern disposed on the same layer as one of the (1-1)-th metal pattern and the (1-2)-th metal pattern.

公开(公告)号：US12131688B2

公开(公告)日：2024-10-29

申请号：US18091340

申请日：2022-12-29

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： Shaozhen Song ,  Thomas Hamish Barter ,  Dale Eugene Zimmerman

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2310/06 ,  G09G2310/08 ,  G09G2320/0209 ,  G09G2320/0693 ,  G09G2354/00 ,  G09G2360/16 ,  G09G2370/04

Abstract: The techniques disclosed herein compensate for crosstalk effects between victim and aggressor emitters, such as for proximity located laser diodes in a scanned laser display system. The data stream associated with a drive signal for an aggressor is decomposed into rising and falling timing and amplitude values that are stored in a history buffer. The lag in timing between a reference timing signal from the victim data stream and the timing values in the history buffer are used to identify compensation factors. The compensation factors, which may be stored in a look-up table and based on prior collected data, are applied to rising and falling amplitudes from the history buffer to product weighted sums. The weighted sums are applied to the data stream for the victim emitter to compensate for crosstalk effects that would occur as a consequence of the aggressor.

公开(公告)号：US12131683B2

公开(公告)日：2024-10-29

申请号：US17497920

申请日：2021-10-09

Applicant: Beijing BOE Display Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Xin Duan ,  Jigang Sun ,  Shaolei Zong ,  Wei Sun

IPC: G09G3/20 ,  G06F1/08 ,  G06F1/12 ,  G06F1/14

CPC classification number: G09G3/2092 ,  G06F1/08 ,  G06F1/12 ,  G06F1/14 ,  G09G2310/08 ,  G09G2340/0435

Abstract: A method for clock calibration is provided. In the technical solution according to the present disclosure, a target driving chip includes a plurality of clock calibration circuits, wherein each of the clock calibration circuits is configured with one clock frequency. Prior to sending a clock calibration signal, a controller sends a reference clock frequency to a driving chip over a configuration instruction, such that the driving chip determines a target clock calibration circuit for clock calibration based on the configuration instruction.

公开(公告)号：US20240355296A1

公开(公告)日：2024-10-24

申请号：US18629944

申请日：2024-04-09

Applicant: NOVATEK Microelectronics Corp.

Inventor： Huan-Teng Cheng

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2340/0435

Abstract: A method of controlling a display panel which performs a scan operation on an image frame with a first scan setting and a second scan setting includes steps of: outputting a start pulse to the display panel when starting the scan operation; outputting a clock signal to the display panel when the scan operation is in the first scan setting; stopping outputting the clock signal to the display panel when the scan operation is in the second scan setting; and restarting to output the clock signal to the display panel when the scan operation is switched to the first scan setting from the second scan setting. The first scan setting and the second scan setting are for display of the display panel.