公开(公告)号：US08569838B2

公开(公告)日：2013-10-29

申请号：US13049862

申请日：2011-03-16

申请人： James Walter Blatchford, Jr. ,  Yong Seok Choi

发明人： James Walter Blatchford, Jr. ,  Yong Seok Choi

IPC分类号： H01L21/70

CPC分类号： H01L29/66484 ,  H01L21/28123 ,  H01L21/823828 ,  H01L27/0207 ,  H01L29/78

摘要： A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of a width near the critical dimension. Off-axis illumination, as used in the photolithography of deep sub-micron critical dimension, is facilitated by the patterned features having a preferred orientation in a common direction, with a pitch constrained to within a relatively narrow range. Interconnects in that same gate level, for example “field poly” interconnects, that run parallel to an array of gate elements are placed within a specified distance range from the ends of the gate elements, or at a distance sufficient to allow sub-resolution assist features.

摘要翻译： 一种在集成电路中制造栅极电极和互连的方法，以及如此制造的集成电路，其具有改进的临界尺寸附近的栅极级互连的工艺裕度。 在深亚微米临界尺寸的光刻中使用的离轴照明通过具有在相同方向上具有优选取向的图案化特征促进，其间距限制在相对较窄的范围内。 在与栅极元件阵列平行的同一栅极级别（例如，“多晶”互连）的互连被放置在从栅极元件的端部指定的距离范围内，或者距离足以允许次级分辨率辅助 特征。