公开(公告)号：US20100082895A1

公开(公告)日：2010-04-01

申请号：US12567624

申请日：2009-09-25

申请人： Jeremy Branscome ,  Michael Corwin

发明人： Jeremy Branscome ,  Michael Corwin

IPC分类号： G06F12/00

CPC分类号： G11C15/00

摘要： A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM.

摘要翻译： 多级内容可寻址存储器（CAM）架构压缩了单个CAM的搜索空间中遇到的冗余，特别是对于网络中的基于流的查找。 目的地址和源地址可以在多级CAM架构的一个级别中独立地与内部等价类相关联，而链接目的地址和源地址的任意类别的流特定属性可以应用于多级CAM的后一级 。

公开(公告)号：US20090254516A1

公开(公告)日：2009-10-08

申请号：US12099133

申请日：2008-04-07

申请人： Krishnan Meiyyappan ,  Liuxi Yang ,  Jeremy Branscome ,  Michael Corwin ,  Ravi Krishnamurthy ,  Kapil Surlaker ,  James Shau ,  Joseph I. Chamdani

发明人： Krishnan Meiyyappan ,  Liuxi Yang ,  Jeremy Branscome ,  Michael Corwin ,  Ravi Krishnamurthy ,  Kapil Surlaker ,  James Shau ,  Joseph I. Chamdani

IPC分类号： G06F7/06 ,  G06F17/30

CPC分类号： G06F17/30442 ,  G06F17/30094 ,  G06F17/30315 ,  G06F17/30492 ,  G06F17/30504

摘要： Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements.

摘要翻译： 本发明的实施例提供数据库的硬件友好索引。 特别地，正向和反向索引被用于允许轻松地遍历主键到外键关系。 被称为命中列表的新颖结构还允许在硬件中容易地扫描各种索引。 提供组索引，用于复杂组密钥定义的灵活支持，如日期范围索引和文本索引。 还可以将复制的重新排列（RRC）添加到组索引中以将随机I / O模式转换为仅需要的列元素的顺序I / O。

公开(公告)号：US08234267B2

公开(公告)日：2012-07-31

申请号：US13048031

申请日：2011-03-15

申请人： Jeremy Branscome ,  Michael Corwin ,  Liuxi Yang ,  Joseph I. Chamdani

发明人： Jeremy Branscome ,  Michael Corwin ,  Liuxi Yang ,  Joseph I. Chamdani

IPC分类号： G06F7/00 ,  G06F17/30

CPC分类号： G06F17/30442

摘要： Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested. The hardware accelerator utilizes hardware-friendly memory addressing, which allows for arithmetic derivation of a physical address from a global database virtual address simply based on a row identifier. The hardware accelerator minimizes memory reads/writes by keeping most intermediate results flowing through IMCs in pipelined and parallel fashion. Furthermore, the hardware accelerator may employ task pipelining and pre-fetch pipelining to enhance its performance.

摘要翻译： 本发明的实施例提供了一种辅助主机数据库系统处理其查询的硬件加速器。 硬件加速器包括能够以机器码数据库指令的形式接收数据库查询/操作任务的专用处理元件，无需软件执行硬件，并将查询/运算结果返回主机系统。 例如，表和列描述符嵌入在机器码数据库指令中。 为了便于安装，硬件加速器采用标准互连，如PCle或HT互连。 处理元件实现了一种新颖的数据流设计和Inter Macro-Op Communication（IMC）数据结构来执行机器码数据库指令。 硬件加速器还可以包括相对大的存储器，以增强所请求的查询/操作任务的硬件执行。 硬件加速器使用硬件友好的存储器寻址，这允许仅仅基于行标识符从全局数据库虚拟地址算术推导物理地址。 硬件加速器通过保持大多数中间结果以流水线和并行方式流过IMC来最小化存储器读/写。 此外，硬件加速器可以采用任务流水线和预取流水线来增强其性能。

公开(公告)号：US20100005077A1

公开(公告)日：2010-01-07

申请号：US12168821

申请日：2008-07-07

申请人： Ravi Krishnamurthy ,  Chi-Young Ku ,  James Shau ,  Chun Zhang ,  Kapil Surlaker ,  Jeremy Branscome ,  Michael Corwin ,  Joseph I. Chamdani

发明人： Ravi Krishnamurthy ,  Chi-Young Ku ,  James Shau ,  Chun Zhang ,  Kapil Surlaker ,  Jeremy Branscome ,  Michael Corwin ,  Joseph I. Chamdani

IPC分类号： G06F17/30

CPC分类号： G06F16/24542

摘要： Embodiments of the present invention generate and optimize query plans that are at least partially executable in hardware. Upon receiving a query, the query is rewritten and optimized with a bias for hardware execution of fragments of the query. A template-based algorithm may be employed for transforming a query into fragments and then into query tasks. The various query tasks can then be routed to either a hardware accelerator, a software module, or sent back to a database management system for execution. For those tasks routed to the hardware accelerator, the query tasks are compiled into machine code database instructions. In order to optimize query execution, query tasks may be broken into subtasks, rearranged based on available resources of the hardware, pipelined, or branched conditionally

摘要翻译： 本发明的实施例生成和优化在硬件中至少部分可执行的查询计划。 在接收到查询后，查询将被重写和优化，以便查询的片段的硬件执行偏差。 可以采用基于模板的算法将查询转换成片段，然后转换为查询任务。 然后可以将各种查询任务路由到硬件加速器，软件模块，或者发送回数据库管理系统以执行。 对于路由到硬件加速器的任务，将查询任务编译为机器码数据库指令。 为了优化查询执行，查询任务可能被分解为子任务，根据硬件的可用资源，流水线或有条件的分支进行重新排列

公开(公告)号：US07606968B2

公开(公告)日：2009-10-20

申请号：US11430389

申请日：2006-05-08

申请人： Jeremy Branscome ,  Michael Corwin

发明人： Jeremy Branscome ,  Michael Corwin

IPC分类号： G06F12/00

CPC分类号： G11C15/00

摘要： A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM.

摘要翻译： 多级内容可寻址存储器（CAM）架构压缩了单个CAM的搜索空间中遇到的冗余，特别是对于网络中的基于流的查找。 目的地址和源地址可以在多级CAM架构的一个级别中独立地与内部等价类相关联，而链接目的地址和源地址的任意类别的流特定属性可以应用于多级CAM的后一级 。

公开(公告)号：US08229918B2

公开(公告)日：2012-07-24

申请号：US13048024

申请日：2011-03-15

申请人： Jeremy Branscome ,  Michael Corwin ,  Liuxi Yang ,  Joseph I. Chamdani

发明人： Jeremy Branscome ,  Michael Corwin ,  Liuxi Yang ,  Joseph I. Chamdani

IPC分类号： G06F7/00 ,  G06F17/30

CPC分类号： G06F17/30442

摘要： Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested. The hardware accelerator utilizes hardware-friendly memory addressing, which allows for arithmetic derivation of a physical address from a global database virtual address simply based on a row identifier. The hardware accelerator minimizes memory reads/writes by keeping most intermediate results flowing through IMCs in pipelined and parallel fashion. Furthermore, the hardware accelerator may employ task pipelining and pre-fetch pipelining to enhance its performance.

公开(公告)号：US20110246432A1

公开(公告)日：2011-10-06

申请号：US13107399

申请日：2011-05-13

申请人： Liuxi Yang ,  Kapil Surlaker ,  Ravi Krishnamurthy ,  Michael Corwin ,  Jeremy Branscome ,  Krishnan Meiyyappan ,  Joseph I. Chamdani

发明人： Liuxi Yang ,  Kapil Surlaker ,  Ravi Krishnamurthy ,  Michael Corwin ,  Jeremy Branscome ,  Krishnan Meiyyappan ,  Joseph I. Chamdani

IPC分类号： G06F17/30

CPC分类号： G06F17/30315

摘要： Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups.

摘要翻译： 本发明的实施例提供了一个或多个能够有效地加速数据库操作的硬件友好的数据结构。 特别地，本发明采用数据库的列存储格式。 在数据库中，列组通过列跳转和用于添加新数据的堆结构存储隐式行ids（RID）和具有列存储和行存储优势的RID至主键列。 固定宽度列压缩允许直接对压缩数据进行硬件数据库处理。 使用全局数据库虚拟地址空间，允许对数据的任何物理地址的算术推导，而不管其位置如何。 还提供了具有令牌比较和排序索引的单词压缩字典，以允许对文本进行高效的基于硬件的搜索。 还提供了一个元组重建过程，允许硬件通过将来自多个列组的数据进行拼接来重建行。

公开(公告)号：US20090254532A1

公开(公告)日：2009-10-08

申请号：US12099131

申请日：2008-04-07

申请人： Liuxi Yang ,  Kapil Surlaker ,  Ravi Krishnamurthy ,  Michael Corwin ,  Jeremy Branscome ,  Krishnan Meiyyappan ,  Joseph I. Chamdani

发明人： Liuxi Yang ,  Kapil Surlaker ,  Ravi Krishnamurthy ,  Michael Corwin ,  Jeremy Branscome ,  Krishnan Meiyyappan ,  Joseph I. Chamdani

IPC分类号： G06F7/00 ,  G06F17/30

CPC分类号： G06F17/30315

摘要： Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups.

摘要翻译： 本发明的实施例提供了一个或多个能够有效地加速数据库操作的硬件友好的数据结构。 特别地，本发明采用数据库的列存储格式。 在数据库中，列组通过列跳转和用于添加新数据的堆结构存储隐式行ids（RID）和RID至主键列，具有列存储和行存储优势。 固定宽度列压缩允许直接对压缩数据进行硬件数据库处理。 使用全局数据库虚拟地址空间，允许对数据的任何物理地址的算术推导，而不管其位置如何。 还提供了具有令牌比较和排序索引的单词压缩字典，以允许对文本进行高效的基于硬件的搜索。 还提供了一个元组重建过程，允许硬件通过将来自多个列组的数据进行拼接来重建行。

公开(公告)号：US20080189252A1

公开(公告)日：2008-08-07

申请号：US11895998

申请日：2007-08-27

申请人： Jeremy Branscome ,  Michael Corwin ,  Liuxi Yang ,  Joseph I. Chamdani

发明人： Jeremy Branscome ,  Michael Corwin ,  Liuxi Yang ,  Joseph I. Chamdani

IPC分类号： G06F17/30 ,  G06F13/00

CPC分类号： G06F17/30442

摘要： Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCIe or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested. The hardware accelerator utilizes hardware-friendly memory addressing, which allows for arithmetic derivation of a physical address from a global database virtual address simply based on a row identifier. The hardware accelerator minimizes memory reads/writes by keeping most intermediate results flowing through IMCs in pipelined and parallel fashion. Furthermore, the hardware accelerator may employ task pipelining and pre-fetch pipelining to enhance its performance.

摘要翻译： 本发明的实施例提供了一种辅助主机数据库系统处理其查询的硬件加速器。 硬件加速器包括能够以机器码数据库指令的形式接收数据库查询/操作任务的专用处理元件，无需软件执行硬件，并将查询/运算结果返回主机系统。 例如，表和列描述符嵌入在机器码数据库指令中。 为了便于安装，硬件加速器采用标准互连，例如PCIe或HT互连。 处理元件实现了一种新颖的数据流设计和Inter Macro-Op Communication（IMC）数据结构来执行机器码数据库指令。 硬件加速器还可以包括相对大的存储器，以增强所请求的查询/操作任务的硬件执行。 硬件加速器使用硬件友好的存储器寻址，这允许仅仅基于行标识符从全局数据库虚拟地址算术推导物理地址。 硬件加速器通过保持大多数中间结果以流水线和并行方式流过IMC来最小化存储器读/写。 此外，硬件加速器可以采用任务流水线和预取流水线来增强其性能。

公开(公告)号：US20080189251A1

公开(公告)日：2008-08-07

申请号：US11895997

申请日：2007-08-27

申请人： Jeremy Branscome ,  Michael Corwin ,  Liuxi Yang ,  James Shau ,  Ravi Krishnamurthy ,  Joseph I. Chamdani

发明人： Jeremy Branscome ,  Michael Corwin ,  Liuxi Yang ,  James Shau ,  Ravi Krishnamurthy ,  Joseph I. Chamdani

IPC分类号： G06F17/30

CPC分类号： G06F16/2453

摘要： Embodiments of the present invention provide processing elements that are capable of performing high level database operations in hardware based on machine code instructions. These processing elements employ a dataflow architecture that operates on data in hardware without interruption or software. A scanning/indexing processing element may comprise logic that analyze database column groups stored in local memory, perform parallel field extraction and comparison, and generates a list of row pointers (row ids or RIDs) referencing those rows whose value(s) satisfy an applied predicate. The scanning/indexing processing may also be used to project database column groups, search and join index structures, and manipulate in-flight metadata flows, composing, merging, reducing, and modifying multi-dimensional lists of intermediate and final results. Furthermore, a scanning/indexing processing element may be used for joins with indexes, like a Group Index, which involves the association of each input tuple with potentially many related data components, in a one-to-many mapping. An XCAM processing element may comprise logic to perform associative database operations, like accumulation and aggregation, sieving, sorting and associative joins.

摘要翻译： 本发明的实施例提供了能够基于机器码指令在硬件中执行高级数据库操作的处理元件。 这些处理元件采用在不中断或软件的情况下对硬件上的数据进行操作的数据流架构。 扫描/索引处理元件可以包括分析存储在本地存储器中的数据库列组，执行并行字段提取和比较的逻辑，并且生成参考其值满足应用的那些行的行指针（行ID或RID）的列表 谓词。 扫描/索引处理也可用于投影数据库列组，搜索和连接索引结构，以及操纵机上元数据流，组合，合并，减少和修改中间和最终结果的多维列表。 此外，扫描/索引处理元件可以用于具有诸如组索引的索引的连接，该索引涉及每个输入元组与潜在的许多相关数据组件的关联，在一对多映射中。 XCAM处理元件可以包括执行关联数据库操作的逻辑，例如累积和聚合，筛选，排序和关联连接。