公开(公告)号：US07809054B2

公开(公告)日：2010-10-05

申请号：US11405997

申请日：2006-04-18

申请人： Juan A. Carballo ,  Hayden C. Cranford, Jr. ,  Gareth J. Nicholls ,  Vernon R. Norman ,  Martin L. Schmatz

发明人： Juan A. Carballo ,  Hayden C. Cranford, Jr. ,  Gareth J. Nicholls ,  Vernon R. Norman ,  Martin L. Schmatz

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L25/03063

摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.

摘要翻译： 公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。 集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。 输入电压被转换为电流并连接到电流求和节点。 由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。 另外，总和电流被积分并转换成电压。 采样器用于基于所得到的电压进行位决定。 采样后，积分器在分析下一位之前被复位。 通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。