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公开(公告)号：US07698802B2
公开(公告)日：2010-04-20
申请号：US12028439
申请日：2008-02-08
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
IPC分类号： G01R31/28
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： A method for manufacturing a calibration device for an active circuit on a chip, comprises: providing an active circuit that is capable of exhibiting a desired electrical characteristic; and providing a calibration mechanism on-chip with the active circuit. The calibration mechanism generates a control output and comprises a device under test (DUT) configured as a replica of at least one segment of the active circuit, and which generates a test output that causes finite adjustments to the control output, based on a comparison of the electrical characteristics exhibited by the DUT with a known electrical characteristic. The method further comprises: attaching to each control input terminal of the active circuit a corresponding control output from the calibration mechanism. The control output of the calibration mechanism dynamically adjusts control input applied to devices of the active circuit to force the active circuit to exhibit the desired electrical characteristic.
摘要翻译： 一种用于制造芯片上的有源电路的校准装置的方法，包括：提供能够呈现所需电特性的有源电路; 并且提供与有源电路片上的校准机制。 所述校准机构产生控制输出，并且包括被配置为所述有源电路的至少一个段的复制品的被测器件（DUT），并且基于所述被测器件的比较，产生对所述控制输出进行有限调整的测试输出 具有已知电特性的DUT所呈现的电特性。 该方法还包括：将有源电路的每个控制输入端连接到校准机构的相应控制输出。 校准机构的控制输出动态调整施加到有源电路的器件的控制输入，以迫使有源电路呈现所需的电特性。
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公开(公告)号：US07418069B2
公开(公告)日：2008-08-26
申请号：US11966438
申请日：2007-12-28
IPC分类号： H04L7/00
CPC分类号： H03L7/091 , H03L7/0814 , H03L7/089 , H04L7/0331
摘要： The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.
摘要翻译： 本发明涉及一种用于根据输入数据信号重新采样时钟信号的时钟数据恢复系统。 时钟数据恢复系统包括用于产生时钟信号的时钟发生器和用于根据相位调整控制信号产生采样相位的相位调整单元。 它还包括可操作以产生输入样本流的数据采样单元和用于从其产生内部早期信号和内部迟滞信号的边缘检测器。 设置相位调整控制单元，用于在早期信号的使用下产生相位调整控制信号，并且延迟信号。 相位调整控制单元可以用外部早/晚信号进给，和/或包括用于传送出口早/晚信号的输出。
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公开(公告)号：US07349498B2
公开(公告)日：2008-03-25
申请号：US10265981
申请日：2002-10-07
CPC分类号： H04L7/0338 , H03K5/1534
摘要： A system and method is disclosed for evaluating a data group of oversampled bits to detect edge transitions and for improving use of information available from a sampled data while maintaining acceptable noise rejection. An edge detection system for receiving a serial data stream includes a sampler for collecting a sample pattern from the serial data stream, the sample pattern including a succession of a plurality of data samples from the data stream with the plurality of data samples including multiple samples during a bit time associated with the data stream; a memory, coupled to the sampler, for storing one or more successive sample patterns; and a correlator, coupled to the memory, for producing a sample condition signal using a set of predefined patterns by comparing the stored sampled patterns to the predefined patterns.
摘要翻译： 公开了一种系统和方法，用于评估过采样比特的数据组以检测边缘转换并改善对采样数据可用信息的使用，同时保持可接受的噪声抑制。 用于接收串行数据流的边缘检测系统包括：采样器，用于从串行数据流收集采样模式，样本模式包括来自数据流的多个数据样本的一系列，其中多个数据样本包括多个样本 与数据流相关联的一段时间; 耦合到采样器的存储器，用于存储一个或多个连续的采样图案; 以及耦合到存储器的相关器，用于通过将所存储的采样图案与预定义图案进行比较，使用一组预定义图案来产生采样条件信号。
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4.发明授权Receiver for clock and data recovery and method for calibrating sampling phases in a receiver for clock and data recovery 失效用于时钟和数据恢复的接收器以及用于校准接收机中的采样相位以用于时钟和数据恢复的方法公开(公告)号：US07149269B2
公开(公告)日：2006-12-12
申请号：US10375286
申请日：2003-02-27
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , H03L7/091 , H03L7/0998 , H04L7/0025 , H04L7/0337
摘要： A receiver for clock and data recovery includes n sampling latches (SL1 . . . SLn) for determining n sample values (SV1 . . . SVn) of a reference signal (Ref2) at n sampling phases (φ1a . . . (φna) having sampling latch inputs and sampling latch outputs. The receiver further includes a phase position analyzer (5) connected to the sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (φ1a . . . φna), if the sample value (SV1 . . . SVn) deviates from a set point and a phase interpolator (9) for generating sampling phases (φ1u . . . φnu). A sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1 . . . SLn) is provided for generating adjusted sampling phases (φ1a . . . φna) depending on the sampling phases (φ1u . . . φnu) and said adjusting signal (AS).
摘要翻译： 用于时钟和数据恢复的接收机包括n个采样锁存器（SL1 ... SLn），用于确定n个采样相位（参见图1a）上的参考信号（Ref 2）的n个采样值（SV1 ... SVn）。 （phina）具有采样锁存输入和采样锁存输出，接收器还包括连接到采样锁存器输出的相位位置分析器（5），用于产生调整信号（AS），用于调整采样相位（phi 1 a。 如果采样值（SV1 ... SVn）偏离设定点，则产生采样相位（phi 1 u。。phinu）的相位插值器（9），连接的采样相位调整单元（6） 其相位位置分析器（5）和相位插值器（9）的输入及其对采样锁存器（SL1 ... SLn）的输出被提供用于产生经调整的采样相位（phi1，...） 取决于采样相位（phi 1 u。。phinu）和所述调整信号（AS）。
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公开(公告)号：US06977558B2
公开(公告)日：2005-12-20
申请号：US10650396
申请日：2003-08-28
申请人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus , Peter R. Seidel
发明人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus , Peter R. Seidel
CPC分类号： H03L7/08 , H03L2207/06
摘要： A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.
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6.发明授权Frame stripping protocol for early token release in a ring communication network 失效在环通信网络中的早期令牌释放的帧去除协议
公开(公告)号：US4932023A
公开(公告)日：1990-06-05
申请号：US368739
申请日：1989-06-20
IPC分类号： H04L12/433
CPC分类号： H04L12/433
摘要： A frame stripping algorithm for use in a ring communication network utilizing early token release wherein multiple frames can exist on the ring at one time. The algorithm introduces two new strip terminating conditions which supplement two of the three conditions applicable to a normal token release scheme. The first of these conditions occurs when the source address in a received message is not the same as the receiving station's address and no code violation errors have been detected. The second condition occurs when the receiving station detects an isolated ending delimiter without a preceding starting delimiter.
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公开(公告)号：US07512177B2
公开(公告)日：2009-03-31
申请号：US11828390
申请日：2007-07-26
IPC分类号： H04B3/46
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern generator. In one aspect, an adjustable capacitance is at least one varactor diode. In another, a pair of varactor diodes are separated by λ/4 lines, an input and an output of the adjustable capacitance is AC-coupled, and the arbitrary waveform generator is configured to adjust the adjustable capacitance through a gaussian noise signal input to the pair of varactor diodes. A deterministic jitter generator may be coupled to the pulse pattern generator. An open-circuited stub line may be input to the pattern generator, a deterministic jitter content number adjustable varying stub line length.
摘要翻译： 装置和方法包括移相器，被配置为调整所述移相器的相移的可调电容，被配置为调节可调电容的任意波形发生器以及耦合到移相器的脉冲图形发生器，所述移相器被配置为 控制脉冲模式发生器。 在一个方面，可调电容是至少一个变容二极管。 另一方面，一对变容二极管由λ/ 4线分开，可调电容的输入和输出是交流耦合的，并且任意波形发生器被配置成通过高斯噪声信号输入到 一对变容二极管。 确定性抖动发生器可以耦合到脉冲图案发生器。 可以向模式发生器输入开路短线，确定性抖动内容数可调，可变长短线长度。
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8.发明申请STRUCTURE FOR ONE-SAMPLE-PER-BIT DECISION FEEDBACK EQUALIZER (DFE) CLOCK AND DATA RECOVERY 审中-公开一次性决策反馈均衡器（DFE）时钟和数据恢复的结构公开(公告)号：US20080240224A1
公开(公告)日：2008-10-02
申请号：US12138214
申请日：2008-06-12
申请人： JUAN A. CARBALLO , Hayden C. Cranford , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： JUAN A. CARBALLO , Hayden C. Cranford , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04L27/01
CPC分类号： H04L25/03885 , H04L25/03057 , H04L2025/03356
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER) is provided. The design generally includes a receiver circuit. The receiver circuit generally includes a decision feedback equalizer (DFE) that produces one sample per bit, and means for automatically self-adjusting the DFE to enable an eye centering process by which peak energy is maintained within the receiver circuit when phase error is a minimum.
摘要翻译： 一种体现在机器可读存储介质中的设计结构，用于设计，制造和/或测试利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的设计 提供接收机并降低误码率（BER）。 该设计通常包括接收器电路。 接收器电路通常包括每位产生一个采样的判决反馈均衡器（DFE），以及用于自动自调整DFE的装置，以便当相位误差最小时能够在接收器电路内保持峰值能量的眼睛对中过程 。
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公开(公告)号：US20080133164A1
公开(公告)日：2008-06-05
申请号：US12021950
申请日：2008-01-29
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译： 公开了一种用于测试高速电路的方法和系统。 该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。 该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。 因此，可以确定高速电路是否在期望的参数内起作用。
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公开(公告)号：US07317777B2
公开(公告)日：2008-01-08
申请号：US10265759
申请日：2002-10-07
IPC分类号： H04L25/00
CPC分类号： H03L7/091 , H04L7/0337
摘要： A system and method for tracking/adapting phase or frequency changes in an incoming serial data stream that may contain significant amounts of noise and/or jitter and may contain relatively long periods of successive univalue data bits. The method includes digitally sampling a received data stream at predefined intervals to produce a data set; estimating when logic transitions occur in the data set; detecting a timing trend represented by the estimated logic transitions; and adjusting a frequency of the first clock so that the timing trend averages approximately zero over a plurality of logic transitions.
摘要翻译： 用于跟踪/调整可能包含大量噪声和/或抖动的输入串行数据流中的相位或频率变化的系统和方法，并且可以包含相对较长的连续的单值数据位。 该方法包括以预定的间隔对接收的数据流进行数字采样以产生数据集; 在数据集中发生逻辑转换时估计; 检测由所估计的逻辑转换表示的定时趋势; 以及调整所述第一时钟的频率，使得所述时序趋势在多个逻辑转换中平均为零。
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