公开(公告)号：US5475242A

公开(公告)日：1995-12-12

申请号：US425250

申请日：1995-04-17

申请人： Jun-ichi Nishizawa ,  Nobuo Takeda ,  Toshiyuki Kishine

发明人： Jun-ichi Nishizawa ,  Nobuo Takeda ,  Toshiyuki Kishine

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/33

CPC分类号： H01L27/092

摘要： A notched insulation gate static induction transistor integrated circuit ording to the present invention comprises an enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to prevent current from flowing in a standby mode, and a depletion enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to cause current to slightly flow in the standby mode. The enhancement mode CMOS logic circuit and the depletion enhancement mode CMOS logic circuit are formed on a major surface of a substrate, and the depletion enhancement mode CMOS logic circuit is used in a circuit in which an average power consumption in a switching operation is higher than that in the standby mode.

摘要翻译： 根据本发明的缺口绝缘栅静电感应晶体管集成电路包括增强模式CMOS逻辑电路，其包括其中确定阈值电压以防止电流在待机模式下流动的缺口绝缘栅静电感应晶体管，以及耗尽增强 模式CMOS逻辑电路，其包括在待机模式下确定阈值电压以使电流稍微流动的缺口绝缘栅静电感应晶体管。 增强模式CMOS逻辑电路和耗尽增强模式CMOS逻辑电路形成在衬底的主表面上，并且耗尽增强模式CMOS逻辑电路用于其中开关操作中的平均功耗高于 在待机模式下。