公开(公告)号：US06986087B2

公开(公告)日：2006-01-10

申请号：US10238570

申请日：2002-09-09

申请人： Kevin Laake ,  Navin Ghisiawan ,  Barry J. Arnold

发明人： Kevin Laake ,  Navin Ghisiawan ,  Barry J. Arnold

IPC分类号： G11R31/28

CPC分类号： G01R31/3185 ,  G01R31/31716

摘要： An embodiment of this invention provides a circuit and method for improving the testability of I/O driver/receivers. First, two separate I/O driver/receiver pads are electrically connected. A bit pattern generator in one of the I/O driver/receivers drives a bit pattern through a driver to the connected pads. The bit pattern is then driven through the receiver of a second I/O driver/receiver to a first clocked register. An identical bit pattern generator in the second I/O driver/receiver then drives an identical bit pattern into a second clocked register. A comparator compares the outputs of these two registers. If the two bit patterns don't match, the comparator signals there is a functional problem with one of the I/O driver/receivers.

摘要翻译： 本发明的实施例提供了一种用于提高I / O驱动器/接收机的可测试性的电路和方法。 首先，两个独立的I / O驱动器/接收器焊盘电连接。 其中一个I / O驱动器/接收器中的位模式发生器通过驱动器将驱动器的位模式驱动到连接的焊盘。 然后，位模式通过第二I / O驱动器/接收器的接收器被驱动到第一时钟寄存器。 第二I / O驱动器/接收器中相同的位模式发生器然后将相同的位模式驱动到第二个时钟寄存器中。 比较器比较这两个寄存器的输出。 如果两个位模式不匹配，则比较器信号与I / O驱动器/接收器之一存在功能问题。

公开(公告)号：US20060161826A1

公开(公告)日：2006-07-20

申请号：US11038733

申请日：2005-01-20

申请人： Navin Ghisiawan ,  Kevin Laake ,  John Howlett

发明人： Navin Ghisiawan ,  Kevin Laake ,  John Howlett

IPC分类号： G01R31/28

CPC分类号： G01R31/318533 ,  G01R31/318566

摘要： A method of modifying data of functional latches of a logic unit during scan chain testing thereof to verify a test case failure of a suspected cell comprises: (a) determining a test case failure in the logic unit through scan chain testing thereof; (b) suspending clocked operations of the logic unit; (c) during suspended clocked operations of the logic unit, performing the following steps: (i) reading logic states of the functional latches; and (ii) modifying the logic state of at least one of the functional latches based on the determined test case failure; (d) restarting clocked operations of the logic unit; and (e) reading logic states of the functional latches resulting from the modification to verify the test case failure of a suspected cell.