公开(公告)号：US20230422498A1

公开(公告)日：2023-12-28

申请号：US18061133

申请日：2022-12-02

Applicant: Kioxia Corporation

Inventor： Daisuke KAWAMURA ,  Ikuya SAIKI ,  Tomonori SAKAGUCHI

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L23/5283

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first contacts arranged in a staircase region on one side in a second direction of a plate-like portion and along the plate-like portion, and individually connected to at least lower conductive layers among the plurality of terraced conductive layers in a first staircase portion; and a plurality of second contacts arranged in the staircase region on another side in the second direction of the plate-like portion and along the plate-like portion, and individually connected to the at least lower conductive layers in the first staircase portion, in which the plurality of first contacts is individually arranged at different positions in the second direction relative to the plate-like portion, depending on the positions in a first direction, and the plurality of second contacts is individually arranged at positions inverted in the second direction from the respective positions of the plurality of first contacts, with respect to the plate-like portion.

公开(公告)号：US20240404948A1

公开(公告)日：2024-12-05

申请号：US18680509

申请日：2024-05-31

Applicant: Kioxia Corporation

Inventor： Daisuke KAWAMURA

IPC: H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor memory device of an embodiment includes: a stacked body including conductive layers stacked apart from each other and having a step portion where the conductive layers are processed in a step-like shape; contacts arranged in the step portion at least on one line in a first direction intersecting with a stacking direction of the stacked body and respectively connected with the conductive layers. A plurality of columnar portions includes first columnar portions having a layer structure different from that of a pillar, and second columnar portions having a same layer structure as that of the pillar. The first columnar portions are arranged on an array at least partially overlapping an array position of the contacts in the first direction. The second columnar portions are arranged on an array away from the array position of the contacts in a second direction intersecting with the stacking direction and the first direction.

公开(公告)号：US20230422499A1

公开(公告)日：2023-12-28

申请号：US18063269

申请日：2022-12-08

Applicant: Kioxia Corporation

Inventor： Gin SUZUKI ,  Daisuke KAWAMURA ,  Tomonori SAKAGUCHI ,  Ikuya SAIKI

IPC: H10B43/27 ,  H01L23/528 ,  H10B43/10

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/11565

Abstract: According to one embodiment, a semiconductor memory device includes a first staircase portion that is arranged in a staircase region at a position that overlaps a plate-like portion in a stacking direction, in which a plurality of conductive layers is terraced in a first direction; and a second staircase portion and a third staircase portion arranged in the staircase region on both sides in a second direction of the plate-like portion, and having structures in each of which the plurality of conductive layers is terraced, and that are mutually inverted in the second direction with respect to the plate-like portion. A plurality of first plugs is individually arranged at different positions in the second direction relative to the plate-like portion, depending on positions in the first direction, and a plurality of second plugs is individually arranged at positions inverted in the second direction from the respective positions of the plurality of first plugs, with respect to the plate-like portion.

公开(公告)号：US20220302045A1

公开(公告)日：2022-09-22

申请号：US17472474

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Daisuke KAWAMURA

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/48

Abstract: A semiconductor device according to an embodiment includes a lower layer wiring and a dummy wiring arranged in a first hierarchy, a contact arranged in a second hierarchy above the first hierarchy and connected to the lower layer wiring, and first and second plate-like portions arranged in the second hierarchy, extending in a stacking direction of each layer belonging to the second hierarchy and in a first direction intersecting with the stacking direction, and sandwiching the contact in a second direction intersecting with the stacking direction and the first direction at a position away from the contact, and the dummy wiring has at least three edges arranged at respective positions overlapping with one of the first and second plate-like portions in the stacking direction, and an orientation in which at least one of the three edges intersects with the first or second plate-like portion differs as viewed from the stacking direction from orientations in which the other edges intersect with the first or second plate-like portion.

公开(公告)号：US20220068950A1

公开(公告)日：2022-03-03

申请号：US17204487

申请日：2021-03-17

Applicant: Kioxia Corporation

Inventor： Daisuke KAWAMURA ,  Go OIKE

IPC: H01L27/11578 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11526

Abstract: A semiconductor device of an embodiment includes first and second structures arranged in a first hierarchy, in which the first and second structures are repeatedly arranged in a first direction along a plane of the first hierarchy, and a distance between geometric centers of the first and second structures in a minimum unit of repetition of the first and second structures differs between a first position and a second position in the first direction.