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公开(公告)号：US20240130121A1
公开(公告)日：2024-04-18
申请号：US18047230
申请日：2022-10-17
IPC分类号： H01L27/11582
CPC分类号： H01L27/11582
摘要： A microelectronic device comprising tiers of alternating dielectric materials and conductive materials, pillars extending through the tiers, and a doped dielectric material adjacent to the tiers. The doped dielectric material comprises a heterogeneous chemical composition comprising one or more dopants. Conductive contact structures are in the doped dielectric material. Additional microelectronic devices, microelectronic systems, and methods of forming microelectronic devices are disclosed.
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2.发明公开公开(公告)号：US20240113012A1
公开(公告)日：2024-04-04
申请号：US17937360
申请日：2022-09-30
发明人： Collin Howder , Yiping Wang
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532 , H01L27/11556 , H01L27/11582
CPC分类号： H01L23/5226 , H01L21/76804 , H01L21/76805 , H01L21/76814 , H01L23/53295 , H01L27/11556 , H01L27/11582
摘要： A microelectronic device comprises a stack structure, a staircase structure, a first liner material, a liner structure, conductive contact structures, and barrier structures. The stack structure comprises vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulative structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The first liner material is on the steps of the staircase structure, and the liner structure on the first liner material. The conductive contact structures extend through the first liner material and the liner structure and to the conductive structures of the stack structure. The barrier structures are between the conductive contact structures and the liner structure vertically span substantially the same tiers of the stack structure as the liner structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
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公开(公告)号：US20240107759A1
公开(公告)日：2024-03-28
申请号：US17951980
申请日：2022-09-23
发明人： LinChun WU , CuiCui KONG , ZhiLiang XIA , ZongLiang HUO
IPC分类号： H01L27/11582 , H01L23/00 , H01L25/065 , H01L25/18
CPC分类号： H01L27/11582 , H01L24/08 , H01L25/0657 , H01L25/18 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
摘要： Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack of conductive layers and insulating layers stacked alternatingly in a first direction. The stack of conductive layers and insulating layers has a first side and a second side in the first direction. The semiconductor device then includes a semiconductor layer at the first side of the stack of conductive layers and insulating layers, and a first isolation structure extending through, in the first direction, the semiconductor layer and a subset of the stack of conductive layers and insulating layers. The subset of the stack of conductive layers and insulating layers includes a first conductive layer. The first isolation structure separates a first portion of the first conductive layer from a second portion of the first conductive layer.
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公开(公告)号：US20240099008A1
公开(公告)日：2024-03-21
申请号：US17945703
申请日：2022-09-15
发明人： Tingting GAO , ZhiLiang XIA , Xiaoxin LIU , Xiaolong DU , Changzhi SUN , Jiayi LIU , ZongLiang HUO
IPC分类号： H01L27/1157 , H01L27/11582
CPC分类号： H01L27/1157 , H01L27/11582
摘要： According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure that includes alternating insulating layers and word line layers. The semiconductor device also includes a first channel structure extending through the stack structure, a first top select gate (TSG) layer over the stack structure, and a second TSG layer over the first TSG layer. The semiconductor device further includes a second channel structure extending through the first and second TSG layers, where the second channel structure is positioned over and coupled to the first channel structure.
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公开(公告)号：US20240098989A1
公开(公告)日：2024-03-21
申请号：US17948549
申请日：2022-09-20
发明人： Zhengliang Xia , Wenbin Zhou , Zongliang Huo , Zhaohui Tang
IPC分类号： H01L27/11556 , H01L27/11519 , H01L27/11526 , H01L27/11565 , H01L27/11573 , H01L27/11582
CPC分类号： H01L27/11556 , H01L27/11519 , H01L27/11526 , H01L27/11565 , H01L27/11573 , H01L27/11582
摘要： A semiconductor device includes a plurality of memory blocks. Each memory block includes a memory deck including interleaved first conductor layers and first dielectric layers, and a separation structure extending to separate two adjacent memory blocks. Each separation structure includes a dielectric stack including interleaved third dielectric layers and fourth dielectric layers. The third dielectric layers are in contact with the first dielectric layers, and the fourth dielectric layers are in contact with the first conductor layers.
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6.发明公开公开(公告)号：US20240081076A1
公开(公告)日：2024-03-07
申请号：US17929911
申请日：2022-09-06
发明人： Sidhartha Gupta , Matthew J. King , Jiewei Chen , Yi Hu
IPC分类号： H01L27/11575 , H01L27/11548 , H01L27/11556 , H01L27/11582
CPC分类号： H01L27/11575 , H01L27/11548 , H01L27/11556 , H01L27/11582
摘要： An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures adjacent to a source, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprising a channel material extending vertically through the stack. The electronic device comprises an additional stack adjacent to the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, pillars extending through the additional stack and adjacent to the strings of memory cells, conductive contacts adjacent to the pillars, and isolation structures laterally intervening between neighboring pillars. The isolation structures exhibit a weave pattern, and portions of the isolation structures are laterally adjacent to and physically contact the conductive contacts. Related memory devices, systems, and methods are also described.
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公开(公告)号：US20240081057A1
公开(公告)日：2024-03-07
申请号：US17929933
申请日：2022-09-06
IPC分类号： H01L27/11582 , H01L21/285 , H01L27/11565
CPC分类号： H01L27/11582 , H01L21/28518 , H01L27/11565
摘要： An electronic device includes a source contact adjacent to a source stack, the source stack including one or more conductive materials, tiers of alternating conductive material and dielectric materials adjacent to the source contact, pillars extending vertically through the tiers and the source contact and at least partially into the source contact, a fill material extending vertically through the tiers to the source contact, and a metal silicide material between the fill material and an upper surface of the source contact. Related devices, systems, and methods are also disclosed.
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公开(公告)号：US20240074180A1
公开(公告)日：2024-02-29
申请号：US17896731
申请日：2022-08-26
发明人： Shasha LIU , Tianhui ZHANG , Min YANG , Xiaoming MAO , Zongliang HUO
IPC分类号： H01L27/11582
CPC分类号： H01L27/11582
摘要： A semiconductor device includes a first stack of alternating first word line layers and first insulating layers over a semiconductor layer. The first stack includes a first array region and a first staircase region adjacent to the first array region. The semiconductor device includes a second stack of alternating second word line layers and second insulating layers, where the second stack includes a second array region over the first array region and a second staircase region adjacent to the second array region and over the first staircase region. The first stack further includes a first transition layer over the first word line layers. The first transition layer includes a first dielectric portion in the first array region that surrounds the first channel structure and a first conductive portion. The first transition layer is disposed between two adjacent first insulating layers of the first insulating layers.
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9.发明公开公开(公告)号：US20240074178A1
公开(公告)日：2024-02-29
申请号：US17823276
申请日：2022-08-30
发明人： John D. Hopkins
IPC分类号： H01L27/11582 , H01L27/11556
CPC分类号： H01L27/11582 , H01L27/11556 , H01L21/28518
摘要： An electronic device comprising one or more blocking regions. The electronic device also comprises a source stack comprising one or more conductive materials, a source contact vertically adjacent to the source stack, and a doped semiconductive material vertically adjacent to the source contact. Tiers of alternating conductive materials and dielectric materials are vertically adjacent to the doped semiconductive material, and pillars extend through the tiers of alternating conductive materials and dielectric materials, the doped semiconductive material, and the source contact and into the source stack. The one or more blocking regions are laterally adjacent to the semiconductive material. Additional electronic devices, electronic systems, and methods are also disclosed.
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公开(公告)号：US20240071932A1
公开(公告)日：2024-02-29
申请号：US17944343
申请日：2022-09-14
IPC分类号： H01L23/535 , H01L23/528 , H01L23/532 , H01L27/11556 , H01L27/11582
CPC分类号： H01L23/535 , H01L23/5283 , H01L23/5329 , H01L27/11556 , H01L27/11582
摘要： A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stack in the stair-step region comprises a cavity comprising a flight of stairs in a vertical cross-section along a first direction. The first tiers are conductive and the second tiers are insulative in a finished-circuitry construction. An insulating lining is formed in the cavity atop treads of the stairs and laterally-over sidewalls of the cavity that are along the first direction. Individual of the treads comprise conducting material of one of the conductive tiers in the finished-circuitry construction. The insulating lining is thicker in a bottom part of the cavity than over the sidewalls of the cavity that are above the bottom part. Insulative material is formed in the cavity directly above the insulating lining. Conductive vias are formed through the insulative material and the insulating lining. Individual of the conductive vias are directly above and directly against the conducting material of the tread of individual of the stairs. Other embodiments, including structure, are disclosed.
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