公开(公告)号：US11380406B2

公开(公告)日：2022-07-05

申请号：US17017726

申请日：2020-09-11

Applicant: Kioxia Corporation

Inventor： Yousuke Hagiwara ,  Kensuke Yamamoto ,  Takeshi Hioka ,  Satoshi Inoue

IPC: G11C7/00 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10

Abstract: In general, according to one embodiment, an output circuit includes first to third power supply lines, a pad, first to second transistors, and a first circuit. A first end of the first transistor is coupled to the first power supply line. A second end of the first transistor is coupled to the pad. A first end of the second transistor is coupled to the second power supply line. A second end of the second transistor is coupled to the pad. The first circuit is coupled to each of the third power supply line and a gate of the first transistor. In a first case, the first circuit applies a fourth voltage to the gate of the first transistor.

公开(公告)号：US11361823B2

公开(公告)日：2022-06-14

申请号：US16831568

申请日：2020-03-26

Applicant: Kioxia Corporation

Inventor： Satoshi Inoue ,  Daisuke Arizono

IPC: G11C16/06 ,  G11C7/10 ,  G11C16/26 ,  G11C11/00 ,  G11C7/04 ,  G11C16/04

Abstract: A method for controlling a memory system, including a controller chip and a non-volatile memory chip which includes a calibration control circuit, a first output buffer, and a first resistance element, includes receiving a read command from the controller, setting a ready/busy signal to a busy state based on the read command, executing a calibration operation which controls an impedance of the first output buffer based on the read command, setting the ready/busy signal to a ready state, and sending data to the control chip in response to the read command. The calibration control circuit calibrates the impedance of the first output buffer circuit by using the first resistance element within a period in which the ready/busy signal is the busy state.

公开(公告)号：US11456023B2

公开(公告)日：2022-09-27

申请号：US17121231

申请日：2020-12-14

Applicant: Kioxia Corporation

Inventor： Yutaka Shimizu ,  Satoshi Inoue ,  Isao Fujisawa ,  Yumi Takada

IPC: G11C11/08 ,  G11C7/10

Abstract: There is provided a semiconductor integrated circuit including an input circuit. The input circuit includes a first amplifier and a second amplifier. The second amplifier is electrically connected to the first amplifier. The second amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a time constant providing circuit. The first transistor has a gate electrically connected to a first node of the first amplifier. The second transistor has a gate electrically connected to a second node of the first amplifier. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The time constant providing circuit is electrically connected between a gate of the third transistor and a drain of the third transistor, a gate of the fourth transistor.