公开(公告)号：US11211013B2

公开(公告)日：2021-12-28

申请号：US17132735

申请日：2020-12-23

Applicant: LG Display Co., Ltd.

Inventor： KwangSoo Kim ,  HongJae Shin ,  JaeKyu Park

IPC: G09G3/3266

Abstract: A gate driving circuit and a display apparatus including the same are disclosed, in which a plurality of gate lines may be driven through one stage circuit. The gate driving circuit includes first to mth stage circuits outputting a plurality of scan signals by dividing the scan signals into a first signal group and a second signal group. The first to mth stage circuits are grouped into k number of stage groups having two adjacent stage circuits, stage circuits of jth stage group (j is a natural number of 1 to k−1) output the scan signals of the first signal group to be earlier than the scan signals of the second signal group, and stage circuits of (j+1)th stage group output the scan signals of the second signal group to be earlier than the scan signals of the first signal group.

公开(公告)号：US11488543B2

公开(公告)日：2022-11-01

申请号：US17560127

申请日：2021-12-22

Applicant: LG Display Co., Ltd.

Inventor： KwangSoo Kim

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A gate driving circuit includes a first gate driving circuit and a second gate driving circuit, wherein the m number of first clock signals input to the first gate driving circuit includes an (n+1)-th clock signal and an (n+k)-th clock signal, and the m number of second clock signals input to the second gate driving circuit includes an (n+2)-th clock signal and an (n+k+1)-th clock signal, where the n is any integer, and the k is a natural number of 3 or more, a high level voltage duration of the (n+1)-th clock signal and a high level voltage duration of the (n+k)-th clock signal do not overlap, and a high level voltage duration of the (n+2)-th clock signal and a high level voltage duration of the (n+k+1)-th clock signal do not overlap.

公开(公告)号：US12051371B2

公开(公告)日：2024-07-30

申请号：US18066759

申请日：2022-12-15

Applicant: LG Display Co., Ltd.

Inventor： KwangSoo Kim ,  YongHo Kim ,  Jaesung Park

IPC: G09G3/3266 ,  G09G3/32

CPC classification number: G09G3/3266 ,  G09G3/32 ,  G09G2310/0267 ,  G09G2310/0291 ,  G09G2310/061

Abstract: According to embodiments of the disclosure, a gate driving circuit and a display device may include four buffer groups for driving 4k scan lines, two common logic units for controlling the four buffer groups, and a common sensing circuit controlling to output a sensing driving scan signal to at least one scan line among the 4k scan lines. Thus, it is possible to allow the gate driving circuit to have a low-area structure and to reduce the bezel area of the display device.

公开(公告)号：US20220208127A1

公开(公告)日：2022-06-30

申请号：US17560127

申请日：2021-12-22

Applicant: LG Display Co., Ltd.

Inventor： KwangSoo Kim

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A gate driving circuit includes a first gate driving circuit and a second gate driving circuit, wherein the m number of first clock signals input to the first gate driving circuit includes an (n+1)-th clock signal and an (n+k)-th clock signal, and the m number of second clock signals input to the second gate driving circuit includes an (n+2)-th clock signal and an (n+k+1)-th clock signal, where the n is any integer, and the k is a natural number of 3 or more, a high level voltage duration of the (n+1)-th clock signal and a high level voltage duration of the (n+k)-th clock signal do not overlap, and a high level voltage duration of the (n+2)-th clock signal and a high level voltage duration of the (n+k+1)-th clock signal do not overlap.