公开(公告)号：US20220059017A1

公开(公告)日：2022-02-24

申请号：US17392876

申请日：2021-08-03

Applicant: LG Display Co., Ltd.

Inventor： ManGyu PARK ,  JinCheol HONG

IPC: G09G3/32 ,  H04L7/033 ,  H04L7/04

Abstract: A display is disclosed where in an optimization mode, the controller transmits a first lock signal having a pulse waveforms to a first source driver circuit among source driver circuits, receives a second lock signal having pulse waveforms from a last source driver circuit that receives the first lock signal, and transmits phase loop fixed data for recovering a frequency and a phase of a clock to each of the source driver circuits when the second lock signal is received, and in the display mode, the controller transmits a first lock signal having a preset voltage level to the first source driver circuit, receives a second lock signal having a plurality of preset voltage levels from a last source driver circuit, and supplies an image signal and control data to each of the source driver circuits when the second lock signal is received.