公开(公告)号：US20230139398A1

公开(公告)日：2023-05-04

申请号：US17974447

申请日：2022-10-26

Applicant: LG Display Co., Ltd.

Inventor： YongHo Kim

IPC: G09G3/3266 ,  G09G3/3233

Abstract: Disclosed are a gate driving circuit including a first gate output buffer circuit and a control circuit, and a display device including the same. The control circuit may include a first transistor connected between a first driving voltage node and a QB node, two second transistors connected in series between the QB node and a second low level voltage node, a third transistor connected between a connection node of the two second transistors and the first driving voltage node, a fourth transistor connected between the gate node of the first transistor and the first driving voltage node, and two fifth transistors connected in series between the gate node of the first transistor and the second low level voltage node. A connection node of the two fifth transistors may be electrically connected to the source node or the drain node of the third transistor.

公开(公告)号：US12283249B2

公开(公告)日：2025-04-22

申请号：US18593260

申请日：2024-03-01

Applicant: LG Display Co., Ltd.

Inventor： Dongmyoung Kim ,  HongJae Shin ,  YongHo Kim

IPC: G09G3/32 ,  G09G3/3266 ,  H10K59/121

Abstract: A display device and a gate driving panel circuit including the same are discussed. The gate driving panel circuit in an example includes an output buffer block configured to receive a clock signal and output a scan signal, and a logic block configured to control respective voltages of a Q node and a QB node electrically connected to the output buffer block. The output buffer block includes a pull-up transistor disposed between a clock node to which the clock signal is input and an output node to which the scan signal is output, and a pull-down transistor disposed between a gate low voltage node to which a gate low voltage is applied and the output node. A gate node of the pull-up transistor is electrically connected to the Q node.

公开(公告)号：US12051371B2

公开(公告)日：2024-07-30

申请号：US18066759

申请日：2022-12-15

Applicant: LG Display Co., Ltd.

Inventor： KwangSoo Kim ,  YongHo Kim ,  Jaesung Park

IPC: G09G3/3266 ,  G09G3/32

CPC classification number: G09G3/3266 ,  G09G3/32 ,  G09G2310/0267 ,  G09G2310/0291 ,  G09G2310/061

Abstract: According to embodiments of the disclosure, a gate driving circuit and a display device may include four buffer groups for driving 4k scan lines, two common logic units for controlling the four buffer groups, and a common sensing circuit controlling to output a sensing driving scan signal to at least one scan line among the 4k scan lines. Thus, it is possible to allow the gate driving circuit to have a low-area structure and to reduce the bezel area of the display device.

公开(公告)号：US11887532B2

公开(公告)日：2024-01-30

申请号：US17974447

申请日：2022-10-26

Applicant: LG Display Co., Ltd.

Inventor： YongHo Kim

IPC: G09G3/32 ,  G09G3/3233

CPC classification number: G09G3/32 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08

Abstract: Disclosed are a gate driving circuit including a first gate output buffer circuit and a control circuit, and a display device including the same. The control circuit may include a first transistor connected between a first driving voltage node and a QB node, two second transistors connected in series between the QB node and a second low level voltage node, a third transistor connected between a connection node of the two second transistors and the first driving voltage node, a fourth transistor connected between the gate node of the first transistor and the first driving voltage node, and two fifth transistors connected in series between the gate node of the first transistor and the second low level voltage node. A connection node of the two fifth transistors may be electrically connected to the source node or the drain node of the third transistor.