公开(公告)号：US20210150972A1

公开(公告)日：2021-05-20

申请号：US17030510

申请日：2020-09-24

Applicant: LG ELECTRONICS INC.

Inventor： Jihoon LEE ,  Jongchan KIM ,  Kyeongryeol PARK ,  Jeonghyu YANG ,  Seoksoo LEE ,  Byungtae CHOI

IPC: G09G3/20 ,  G09G3/3208

Abstract: The present disclosure relates to a signal processing device and an image display apparatus including the same. A signal processing device according to an embodiment of the present disclosure includes: an input interface to receive an image signal; a first image processor to generate first image frame data based on the image signal; a second image processor to generate second image frame data scaled down from the first image frame data based on the image signal; and an output interface to receive the first image frame data from the first image processor and the second image frame data from the second image processor and to output the first image frame data and the second image frame data, wherein the first image frame data output from the output interface is more delayed than the second image frame data output from the output interface. Accordingly, a timing controller may accurately and rapidly perform signal processing for a panel.

公开(公告)号：US20230298508A1

公开(公告)日：2023-09-21

申请号：US18321660

申请日：2023-05-22

Applicant: LG ELECTRONICS INC.

Inventor： Jihoon LEE ,  Jongchan KIM ,  Kyeongryeol PARK ,  Jeonghyu YANG ,  Seoksoo LEE ,  Byungtae CHOI

IPC: G09G3/20 ,  G09G3/3208

CPC classification number: G09G3/2096 ,  G09G3/3208 ,  G09G2310/08 ,  G09G2360/18

Abstract: The present disclosure relates to a signal processing device and an image display apparatus including the same. A signal processing device according to an embodiment of the present disclosure includes: an input interface to receive an image signal; a first image processor to generate first image frame data based on the image signal; a second image processor to generate second image frame data scaled down from the first image frame data based on the image signal; and an output interface to receive the first image frame data from the first image processor and the second image frame data from the second image processor and to output the first image frame data and the second image frame data, wherein the first image frame data output from the output interface is more delayed than the second image frame data output from the output interface. Accordingly, a timing controller may accurately and rapidly perform signal processing for a panel.

公开(公告)号：US20220223097A1

公开(公告)日：2022-07-14

申请号：US17657090

申请日：2022-03-29

Applicant: LG ELECTRONICS INC.

Inventor： Jihoon LEE ,  Jongchan KIM ,  Kyeongryeol PARK ,  Jeonghyu YANG ,  Seoksoo LEE ,  Byungtae CHOI

IPC: G09G3/20 ,  G09G3/3208

Abstract: The present disclosure relates to a signal processing device and an image display apparatus including the same. A signal processing device according to an embodiment of the present disclosure includes: an input interface to receive an image signal; a first image processor to generate first image frame data based on the image signal; a second image processor to generate second image frame data scaled down from the first image frame data based on the image signal; and an output interface to receive the first image frame data from the first image processor and the second image frame data from the second image processor and to output the first image frame data and the second image frame data, wherein the first image frame data output from the output interface is more delayed than the second image frame data output from the output interface. Accordingly, a timing controller may accurately and rapidly perform signal processing for a panel.

公开(公告)号：US20150293609A1

公开(公告)日：2015-10-15

申请号：US14614648

申请日：2015-02-05

Applicant: LG ELECTRONICS INC.

Inventor： Wooseong CHUNG ,  Byungtae CHOI ,  Chongsok KIM ,  Seoksoo LEE ,  Woonghyeon KIM ,  Jaehan PARK

IPC: G06F3/033

CPC classification number: G06F3/033 ,  G06F3/038 ,  G06F3/0487 ,  G06F3/04892 ,  H04N5/44513 ,  H04N7/088 ,  H04N2005/4428

Abstract: A multimedia device and method of controlling a cursor thereof are disclosed, by which a frequency of the cursor can be increased without system extension. The present invention includes receiving a cursor display signal from an input device, generating a location information of a cursor and an image information of the cursor in accordance with the received cursor display signal, embedding the generated location information of the cursor in the video signal, and displaying the image information of the cursor based on the location information of the cursor embedded in the video signal.

Abstract translation: 公开了一种控制其光标的多媒体设备和方法，通过该方法可以在不进行系统扩展的情况下增加光标的频率。 本发明包括从输入装置接收光标显示信号，根据接收到的光标显示信号产生光标的位置信息和光标的图像信息，将生成的光标的位置信息嵌入到视频信号中， 以及基于嵌入在视频信号中的光标的位置信息来显示光标的图像信息。

公开(公告)号：US20190279595A1

公开(公告)日：2019-09-12

申请号：US16031367

申请日：2018-07-10

Applicant: LG ELECTRONICS INC.

Inventor： Kyounghoon JANG ,  Byungtae CHOI

IPC: G09G5/00 ,  G06T3/40

Abstract: A display device according to an embodiment of the present invention may process an input image with higher resolution than allowed easily without reconfiguring a hardware system through an image processing unit which divides input image data with first resolution into image blocks of an acceptable size and generating processed image data with second resolution lower than the first resolution.

公开(公告)号：US20190221186A1

公开(公告)日：2019-07-18

申请号：US16111111

申请日：2018-08-23

Applicant: LG ELECTRONICS INC.

Inventor： Kyounghoon JANG ,  Kwangyeon RHEE ,  Byungtae CHOI

IPC: G09G5/00 ,  G09G5/395

Abstract: Disclosed are an image display device and an image processing method thereof. A signal processing method of the image display device according to the present invention is a signal processing method of an image display device configured to receive an image having a varied vertical synchronization signal, including detecting an input synchronization signal using an input image clock, extracting an input vertical synchronization signal from the input synchronization signal, delaying the input vertical synchronization signal by a reference value of an output clock, continuously tracking a falling region of the delayed input vertical synchronization signal, and finally generating an output synchronization signal in which a vertical front porch is varied.