公开(公告)号：US20040108987A1

公开(公告)日：2004-06-10

申请号：US10726518

申请日：2003-12-04

Applicant: LG.Philips LCD Co., Ltd.

Inventor： Jae-Deok Park ,  Byeong-Koo Kim ,  Kee-Jong Kim

IPC: G09G003/36

CPC classification number: G09G3/3688 ,  G09G3/3655 ,  G09G3/3677 ,  G09G2300/0876 ,  G09G2320/0257

Abstract: A system for reducing an OFF-current in a thin film transistor of a liquid crystal display device includes gate and data lines crossing each other, a pixel thin film transistor including gate, source and drain electrodes, the gate electrode connected to the gate line and the source electrode connected to the data line, a liquid crystal capacitor connected to the drain electrode of the pixel thin film transistor, a first switch thin film transistor connected to a first end of the data line, a second switch thin film transistor connected to a first end of the gate line, a first voltage source electrically connected to the drain electrode of the pixel thin film transistor, a second voltage source connected to a source electrode of the first switch thin film transistor, a third voltage source connected to gate electrodes of the first and second switch thin film transistors, and a fourth voltage source connected to a source electrode of the second switch thin film transistor.

Abstract translation: 一种用于降低液晶显示装置的薄膜晶体管中的截止电流的系统包括彼此交叉的栅极和数据线，包括栅极，源极和漏极的像素薄膜晶体管，连接到栅极线的栅电极和 连接到数据线的源电极，连接到像素薄膜晶体管的漏电极的液晶电容器，连接到数据线的第一端的第一开关薄膜晶体管，连接到数据线的第一端的第二开关薄膜晶体管 栅极线的第一端，与像素薄膜晶体管的漏电极电连接的第一电压源，连接到第一开关薄膜晶体管的源电极的第二电压源，连接到第一开关薄膜晶体管的栅电极的第三电压源 第一和第二开关薄膜晶体管，以及连接到第二开关薄膜晶体管的源电极的第四电压源。

公开(公告)号：US20040227718A1

公开(公告)日：2004-11-18

申请号：US10747688

申请日：2003-12-30

Applicant: LG.Philips LCD Co., Ltd.

Inventor： Jae-Deok Park

IPC: G09G003/36

CPC classification number: G11C19/184 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G11C19/00 ,  G11C19/28

Abstract: A shift register includes stages shifting an input signal with phase-delayed control signals and first and second supply voltages, and for applying shifted input signals as output signals and as input signals of succeeding stages. Each of the stages includes a first controller selectively applying an input signal and a first supply voltage to a first node between first to third transistors; a second controller selectively applying the first and second supply voltages to a second node between fourth and fifth transistors; and an output buffer selectively applying a predetermined control signal and the first supply voltage as an output signal to a stage output line between sixth and seventh transistors, wherein the fifth transistor may be turned on to sustain a voltage present at the second node equal to the first supply voltage when the fourth transistor is turned off.

Abstract translation: 移位寄存器包括通过相位延迟的控制信号和第一和第二电源电压对输入信号进行移位，并且用于将移位的输入信号作为输出信号和作为后级的输入信号。 每个级包括第一控制器，其选择性地将输入信号和第一电源电压施加到第一至第三晶体管之间的第一节点; 第二控制器选择性地将第一和第二电源电压施加到第四和第五晶体管之间的第二节点; 以及输出缓冲器，其选择性地将预定控制信号和所述第一电源电压作为输出信号施加到第六和第七晶体管之间的级输出线，其中所述第五晶体管可以导通以维持存在于所述第二节点处的电压等于 第四晶体管关断时的第一电源电压。