Active matrix display with dual driving modes

    公开(公告)号:US10037735B2

    公开(公告)日:2018-07-31

    申请号:US14080209

    申请日:2013-11-14

    申请人: E INK CORPORATION

    发明人: Karl R. Amundson

    IPC分类号: G09G3/34 G02B26/00 G02F1/167

    摘要: An active matrix electro-optic display (100) includes capacitor electrodes (110, 112) associated with the pixel electrodes (106, 108) so that the pixel electrode and its associated capacitor electrode form a capacitor. The display (100) also includes switching means (120) having one position in which each capacitor electrode (110, 112) is electrically connected to the light-transmissive front electrode (102) of the display (100) and a second position in which each capacitor electrode (110, 112) is electrically connected to a voltage source having a voltage independent of the voltage on the light-transmissive electrode.

    GATE DRIVING CIRCUIT
    4.
    发明申请

    公开(公告)号:US20180174503A1

    公开(公告)日:2018-06-21

    申请号:US15840927

    申请日:2017-12-13

    IPC分类号: G09G3/20 G11C19/28

    摘要: The gate driving circuit includes a shift register including a plurality of stages. An n-th stage among the plurality of stages includes: a pull-up switching element outputting a first clock to an output node in accordance with a voltage in a Q node, a pull-down switching element outputting a gate low voltage VGL to the output node in accordance with a voltage in a QB node, and a logic unit inverting and outputting a voltage in the Q node and a voltage in the QB node. The logic unit includes a first switching element including a gate to which a fourth clock is input and being between a start voltage line which supplies a start voltage and the Q node, a second switching element including a gate connected to the Q node and being connected to the QB node, a third switching element being between the second switching element and a gate low voltage line which supplies the gate low voltage, a fourth switching element including a gate to which a third clock is input and being between a gate high voltage line which supplies a gate high voltage and the QB node, a fifth switching element including a gate connected to the QB node and being between the Q node and the gate low voltage line, a first capacitor between the Q node and the output node, and a second capacitor between the gate low voltage line and the gate of the pull-down switching element.

    Method for driving liquid crystal display device

    公开(公告)号:US09852703B2

    公开(公告)日:2017-12-26

    申请号:US12976431

    申请日:2010-12-22

    申请人: Hiroyuki Miyake

    发明人: Hiroyuki Miyake

    IPC分类号: G09G3/36

    摘要: An object is to suppress deterioration of a displayed image even when a refresh rate is reduced in displaying a still image. A liquid crystal display device includes a pixel transistor electrically connected to a pixel electrode, and a capacitor having one electrode electrically connected to the pixel electrode and the other electrode electrically connected to a capacitor line. The pixel transistor is turned on and a voltage based on an image signal is supplied to the pixel electrode, and then, the pixel transistor is turned off so that a holding period during which the pixel electrode holds the voltage based on the image signal starts. A holding signal corresponding to change of the voltage based on the image signal in the pixel electrode in the holding period is supplied to the capacitor line so that a potential of the pixel electrode is constant.

    Pixel, display device comprising the same and having an initialization period and driving method thereof

    公开(公告)号:US09842537B2

    公开(公告)日:2017-12-12

    申请号:US14991900

    申请日:2016-01-08

    IPC分类号: G09G3/32 G09G3/3225

    摘要: A display device includes: a display unit including a plurality of pixels, each of the pixels including: an OLED; and a driving transistor to supply current to an anode of the OLED according to a voltage applied to a gate of the driving transistor and a power supply voltage; a scan driver to supply scan signals to the pixels; an initialization driver to supply initializing signals to the pixels; a data driver to supply data signals to the pixels; light emission drivers to supply first and second light emission signals to the pixels; and a power supply to supply the power supply voltage and an initialization voltage to the pixels, wherein the initialization voltage is supplied to the anode during a first period, and the power supply voltage corresponding to a threshold voltage of the driving transistor is supplied to the gate during a first sub-period of the first period.

    Array substrate, liquid crystal display panel and method for driving the same

    公开(公告)号:US09829760B2

    公开(公告)日:2017-11-28

    申请号:US14417707

    申请日:2015-01-20

    发明人: Xiaohui Yao

    摘要: Related to is an array substrate, a liquid crystal display panel and a method for driving the liquid crystal display panel. In the array substrate, each pixel unit thereon comprises a main-area electrode, a sub-area electrode and a sharing capacitor. a control terminal of a sharing control switch connecting the sharing capacitor to the sub-area electrode is connected, via a first control switch, to a scan line correlated with an Nth pixel unit which is arranged in a scanning direction and counted from a present pixel unit, and via a second control switch to a scan line correlated with the present pixel unit. Under a two-dimensional scanning mode, the first control switch is configured to be turned on when at least there is a scan signal on a scan line to which the first control switch is connected, and the second control switch is configured to be turned off when at least there is a scan signal on both a scan line to which the second control switch is connected and on a scan line to which a first control switch of the same stage as the second control switch is connected. Under a three-dimensional scanning mode, the first control switch is configured to be turned off when at least there is a scan signal on the scan line to which the first control switch is connected, and the second control switch is configured to be turned on when at least there is a scan signal on the scan line to which the second control switch is connected.