公开(公告)号：US20230109723A1

公开(公告)日：2023-04-13

申请号：US17706232

申请日：2022-03-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Meng-Yen WU ,  Teng-Hao YEH

IPC: H01L27/11573 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11526

Abstract: Circuit structures to improve manufacturing yield in complex 3D circuits have a first stack of conductors and a second stack of conductors having memory regions and contact regions. Conductors of the first stack have stepped arrangement in the contact region to provide landing areas on the conductors. Connecting circuits connect the landing areas of conductive layers in the first stack to through-stack conductors in vias in the second stack, to connect to circuitry below the stack. The memory regions include arrays of vertical memory pillars. The connecting circuits include interlayer connectors contacting landing areas in the first stack, extending to patterned conductors over the first and second stacks. The patterned conductors can include links from interlayer connectors of the first stack to through-stack connectors of the second stack. The circuit structure can include a plurality of structural vertical pillars in the contact region of the first stack.