公开(公告)号：US20240386976A1

公开(公告)日：2024-11-21

申请号：US18199308

申请日：2023-05-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE ,  Teng-Hao YEH ,  Wei-Chen CHEN

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: An array of memory cells includes a resistive component disposed in thermal communication with a group of memory cells in the array of memory cells. A capacitor and a circuit to cause discharge of the capacitor via the resistive component induces thermal anneal of the group of memory cells. A charge pump and a circuit to enable the charge pump to precharge the capacitor can be used. The charge pump, the capacitor and the array of memory cells can be disposed on a single integrated circuit. The group of memory cells can be arranged in a 3D stack having multiple levels, and the resistive component can be “snaked” through the stack. The thermal anneal can be executing in timing coordination with erase operations in flash memory.

公开(公告)号：US20230109723A1

公开(公告)日：2023-04-13

申请号：US17706232

申请日：2022-03-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Meng-Yen WU ,  Teng-Hao YEH

IPC: H01L27/11573 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11526

Abstract: Circuit structures to improve manufacturing yield in complex 3D circuits have a first stack of conductors and a second stack of conductors having memory regions and contact regions. Conductors of the first stack have stepped arrangement in the contact region to provide landing areas on the conductors. Connecting circuits connect the landing areas of conductive layers in the first stack to through-stack conductors in vias in the second stack, to connect to circuitry below the stack. The memory regions include arrays of vertical memory pillars. The connecting circuits include interlayer connectors contacting landing areas in the first stack, extending to patterned conductors over the first and second stacks. The patterned conductors can include links from interlayer connectors of the first stack to through-stack connectors of the second stack. The circuit structure can include a plurality of structural vertical pillars in the contact region of the first stack.

公开(公告)号：US20230317143A1

公开(公告)日：2023-10-05

申请号：US18206422

申请日：2023-06-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Cheng-Lin SUNG ,  Yung-Feng LIN

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C16/10 ,  G11C16/28

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4099 ,  G11C16/102 ,  G11C16/28

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US20230007890A1

公开(公告)日：2023-01-12

申请号：US17368705

申请日：2021-07-06

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Cheng-Lin SUNG ,  Yung-Feng LIN

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4074 ,  G11C16/10 ,  G11C16/28

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US20220181347A1

公开(公告)日：2022-06-09

申请号：US17113190

申请日：2020-12-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei HU ,  Teng-Hao YEH

IPC: H01L27/11582 ,  H01L21/768 ,  G11C16/08

Abstract: A memory device includes a stacked structure and at least one first element structure. The stacked structure is in a memory array region and a staircase contact region. The stacked structure includes first conductive layers and a second conductive layer arranged in a longitudinal direction. The memory array region and the staircase contact region are arranged in a first lateral direction. The at least one first element structure passes through the first conductive layers and the second conductive layer along the longitudinal direction. The first conductive layers surround a sidewall surface of the at least one first element structure. The second conductive layer includes conductive portions arranged in a second lateral direction. The conductive portions are completely separated from each other by the at least one first element structure. The first lateral direction is different from the second lateral direction.

公开(公告)号：US20220013180A1

公开(公告)日：2022-01-13

申请号：US17105669

申请日：2020-11-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Tzu-Hsuan HSU ,  Po-Kai HSU ,  Teng-Hao YEH ,  Hang-Ting LUE

IPC: G11C16/26 ,  G11C16/14

Abstract: Provided is an operation method for a memory device, the operation method comprising: performing an erase operation; performing a verify-read operation on a memory cell to generate a cell current, the memory cell including a first transistor and a second transistor; checking whether the cell current is lower than a first cell current threshold; when the cell current is not lower than the first cell current threshold, increasing a memory gate voltage until the cell current is lower than the first cell current threshold, wherein the memory gate voltage is applied to the first transistor; fixing the memory gate voltage and increasing a drain voltage; checking whether the cell current is lower than a second cell current threshold; and if the cell current is not lower than the second cell current threshold, increasing the drain voltage until the cell current is lower than the second cell current threshold.

公开(公告)号：US20250078893A1

公开(公告)日：2025-03-06

申请号：US18240852

申请日：2023-08-31

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Dai-Ying LEE ,  Teng-Hao YEH ,  Wei-Chen CHEN ,  Rachit DOBHAL ,  Zefu ZHAO ,  Chee-Wee LIU

IPC: G11C11/22 ,  G11C5/06 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20

Abstract: The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.

公开(公告)号：US20220068957A1

公开(公告)日：2022-03-03

申请号：US17009968

申请日：2020-09-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao YEH ,  Chih-Wei HU ,  Hang-Ting LUE ,  Guan-Ru LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/522

Abstract: A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

公开(公告)号：US20210242228A1

公开(公告)日：2021-08-05

申请号：US16782953

申请日：2020-02-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei HU ,  Teng-Hao YEH ,  Yu-Wei JIANG

IPC: H01L27/11565 ,  H01L27/11582

Abstract: A memory device comprises a stack of patterned conductor layers, at least a plurality of the layers comprising conductive strips including strips continuous with a pad and other strips isolated from the pad. An array of vertical pillars extends through the stack of patterned conductor layers, wherein memory cells are disposed at cross-points between the vertical pillars and patterned conductor layers. The array has an array boundary proximal to the pad. A first set of isolation blocks extends through the plurality of patterned conductor layers separating the strips continuous with the pad from the other strips isolated from the pad. A second set of isolation blocks inside the array boundary extends through the plurality of patterned conductor layers isolating the other strips from the pad.

公开(公告)号：US20200234770A1

公开(公告)日：2020-07-23

申请号：US16254933

申请日：2019-01-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao YEH ,  Yi Ching LIU

IPC: G11C16/24 ,  H03K19/20 ,  G11C16/04 ,  G11C16/30

Abstract: A memory device is described with NAND strings and corresponding BL connected to SSL, a first power supply circuit, a second power supply circuit to distribute a higher supply voltage than the first power supply circuit, and a page buffer that generates program/inhibit outputs having a level between the first power supply voltage and a first reference voltage. Data line drivers drive nodes coupled to corresponding BL with a first voltage or a second voltage between the second power supply voltage and a second reference voltage. A data line driver includes a first switch transistor connected between the data line node and the second power supply circuit, a second switch transistor between the data line node and the second voltage reference, and a boost circuit to boost the gate of the first switch transistor above the first supply voltage level to turn on the first switch transistor.