公开(公告)号：US12143249B2

公开(公告)日：2024-11-12

申请号：US18116314

申请日：2023-03-02

Applicant: MEDIATEK INC.

Inventor： Deng-Fu Weng ,  Yu-Ting Liu ,  Che-Yu Chiang ,  Chung-Hsien Tsai ,  Huai-Mao Weng

IPC: H04L25/06 ,  H04L1/00 ,  H04L25/03

Abstract: An error detection and correction device includes a decision-feedback equalizer (DFE), a decision circuit, an error detection circuit, and an error correction circuit. The DFE equalizes a data signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a symbol decision signal. The error detection circuit performs forward error detection at symbol positions of consecutive symbols included in the symbol decision signal to detect a head position of suspicious error that affects at least one symbol in the symbol decision signal. The error correction circuit performs error correction upon the symbol decision signal in response to the head position of the suspicious error that is detected by the error detection circuit.

公开(公告)号：US12237949B2

公开(公告)日：2025-02-25

申请号：US18369798

申请日：2023-09-18

Applicant: MEDIATEK INC.

Inventor： Chung-Hsien Tsai ,  Che-Yu Chiang ,  Yu-Ting Liu ,  Tsung-Lin Lee ,  Chia-Sheng Peng ,  Ting-Ming Yang

IPC: H04L25/03 ,  H04L25/49

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

公开(公告)号：US20240129167A1

公开(公告)日：2024-04-18

申请号：US18369798

申请日：2023-09-18

Applicant: MEDIATEK INC.

Inventor： Chung-Hsien Tsai ,  Che-Yu Chiang ,  Yu-Ting Liu ,  Tsung-Lin Lee ,  Chia-Sheng Peng ,  Ting-Ming Yang

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/49

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

公开(公告)号：US20230308322A1

公开(公告)日：2023-09-28

申请号：US18116314

申请日：2023-03-02

Applicant: MEDIATEK INC.

Inventor： Deng-Fu Weng ,  Yu-Ting Liu ,  Che-Yu Chiang ,  Chung-Hsien Tsai ,  Huai-Mao Weng

IPC: H04L25/06 ,  H04L1/00 ,  H04L25/03

CPC classification number: H04L25/061 ,  H04L1/0013 ,  H04L25/03267

Abstract: An error detection and correction device includes a decision-feedback equalizer (DFE), a decision circuit, an error detection circuit, and an error correction circuit. The DFE equalizes a data signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a symbol decision signal. The error detection circuit performs forward error detection at symbol positions of consecutive symbols included in the symbol decision signal to detect a head position of suspicious error that affects at least one symbol in the symbol decision signal. The error correction circuit performs error correction upon the symbol decision signal in response to the head position of the suspicious error that is detected by the error detection circuit.