公开(公告)号：US20240333559A1

公开(公告)日：2024-10-03

申请号：US18191851

申请日：2023-03-28

申请人： PARADE TECHNOLOGIES, LTD

发明人： Canruo Ying

IPC分类号： H04L25/03 ,  H03H17/02

CPC分类号： H04L25/03057 ,  H03H17/02 ,  H03H2017/0081

摘要： This application discloses adaptively setting feed-forward equalization (FFE) for a data communication channel. An equalization signal is generated using a finite impulse response (FIR) filter that has a plurality of FIR coefficients configured to be defined by one of a plurality of preset configurations. A lookup table has a plurality of rows, and each row is associated with a different preset configuration of the FIR coefficients and identifies a subset of respective preset configurations corresponding to a subset of FIR coefficients. In some implementations, a temporal sequence of preset configurations of the FIR coefficients is selected from the lookup table, until a predefined equalization criterion is satisfied. In some implementations, residual errors are determined and correspond to signal samples of the equalization signal, and a sequence of preset configurations of the FIR coefficients is selected from the lookup table based on the residual errors.

公开(公告)号：US20240305507A1

公开(公告)日：2024-09-12

申请号：US18584986

申请日：2024-02-22

申请人： Micron Technology, Inc.

发明人： Chulkyu Lee ,  Timothy M. Hollis

IPC分类号： H04L25/03 ,  G06F13/16

CPC分类号： H04L25/03267 ,  G06F13/1668 ,  H04L25/03057

摘要： Methods, apparatuses, and systems related to an apparatus for managing on-die inter-symbol interference (ISI) are described. The apparatus may include (1) a single communication path with a set of drivers and (2) an on-die ISI prevention circuit coupled to the communication path in parallel. The single communication path may be used to propagate a slower speed signal and a higher speed signal. The on-die ISI prevention circuit may be configured to adjust the propagated signal for one of the speeds to reduce the ISI in the communicated signal.

公开(公告)号：US12074623B2

公开(公告)日：2024-08-27

申请号：US18144342

申请日：2023-05-08

申请人： Rambus Inc.

发明人： Masum Hossain ,  Nhat Nguyen ,  Yikui Jen Dong ,  Arash Zargaran-Yazd ,  Wendemagegnehu Beyene

IPC分类号： H04B1/12 ,  H04L25/02 ,  H04L25/03 ,  H04L25/49 ,  H04L27/00 ,  H04L27/01 ,  H04L27/06

CPC分类号： H04B1/123 ,  H04B1/12 ,  H04L25/0264 ,  H04L25/03057 ,  H04L25/03076 ,  H04L25/03133 ,  H04L25/4917 ,  H04L27/00 ,  H04L27/01 ,  H04L27/06

摘要： Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

公开(公告)号：US12057974B2

公开(公告)日：2024-08-06

申请号：US18112401

申请日：2023-02-21

申请人： NVIDIA Corporation

发明人： Vishnu Balan ,  Viswanath Annampedu ,  Pervez Mirzra Aziz

IPC分类号： H04L25/03

CPC分类号： H04L25/03057

摘要： A receiver includes a decision feed forward equalization (DFFE) system that generates, based on a digital signal that includes at least one intersymbol interference (ISI) value introduced by a communication channel, a detected signal including a set of detected symbol values. The DFFE system cancels the at least one ISI value from the detected signal using the set of estimated transmitted symbols and a set of tap coefficients to obtain a compensated signal and a set of compensated symbol values.

公开(公告)号：US20240223417A1

公开(公告)日：2024-07-04

申请号：US18351366

申请日：2023-07-12

申请人： Seoul National University R&DB Foundation

发明人： Jaeyoon KIM ,  Hyunkyu PARK ,  Suhwan KIM

IPC分类号： H04L27/01 ,  H03F3/45 ,  H04L25/02 ,  H04L25/03

CPC分类号： H04L27/01 ,  H03F3/45475 ,  H04L25/0272 ,  H04L25/03057

摘要： An equalizer includes an amplifying adder configured to generate an output signal by operating differential input signals and a signal generated by applying an equalization coefficient to a post data signal; and a comparator configured to generate a current data signal by sampling the output signal according to a clock signal, wherein the amplifying adder has a maximum gain when a difference of the differential input signals is within a predetermined range.

公开(公告)号：US11979264B1

公开(公告)日：2024-05-07

申请号：US18092756

申请日：2023-01-03

申请人： Cadence Design Systems, Inc.

发明人： Riju Biswas ,  Abhishek Shrivastava

IPC分类号： H04L25/03

CPC分类号： H04L25/03878 ,  H04L25/03057

摘要： Methods and systems are provided for processing a signal over a serial link. The methods and systems receive, by an adjustable filter, a serial input signal, the adjustable filter configured to set a corner frequency of a channel response and a gain of the channel response, the adjustable filter adding a zero to the channel response before to a pole of the serial input signal. The methods and systems selectively apply, by a bandwidth booster component, compensation to signal attenuation of the serial input signal in a first mode of operation and of one or more test signals in a second mode of operation of a serial link receiver. The methods and systems generate, by one or more continuous time linear equalizers configured to receive on an output of the bandwidth booster, one or more output signals of the receiver based on an output signal from the bandwidth booster component.

公开(公告)号：US11973623B2

公开(公告)日：2024-04-30

申请号：US17834563

申请日：2022-06-07

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kyeongjoon Ko ,  Hanseok Kim ,  Jaehyun Park ,  Junhan Bae ,  Gyeongseok Song ,  Jongjae Ryu

IPC分类号： H04L25/03 ,  H04B1/16

CPC分类号： H04L25/03057 ,  H04B1/16 ,  H04L25/03878 ,  H04L2025/03445

摘要： A latch circuit and an equalizer including the same are provided. The equalizer includes: an even data path configured to receive a reception data signal and including a first summing circuit and a first latch circuit; and an odd data path configured to receive the reception data signal and including a second summing circuit and a second latch circuit. An even data signal output from the first latch circuit is configured to be input to the second summing circuit, and an odd data signal output from the second latch circuit is configured to be input to the first summing circuit. Each of the first latch circuit and the second latch circuit includes a latch and a multiplexer.

公开(公告)号：US20240121139A1

公开(公告)日：2024-04-11

申请号：US18532553

申请日：2023-12-07

申请人： Texas Instruments Incorporated

发明人： Raghu Ganesan ,  Kalpesh Rajai

IPC分类号： H04L25/03

CPC分类号： H04L25/03057 ,  H04L25/03267

摘要： Disclosed embodiments include a decision feedback equalizer (DFE) comprising an N-bit parallel input adapted to be coupled to a communication channel and configured to receive consecutive communication symbols, a first DFE path including a first path input configured to receive communication symbols, and a first adder having a first adder input coupled to the first path input. There is a first DFE filter having outputs responsive to the first DFE filter inputs, the outputs coupled to the second adder input. The DFE includes a first path having a first slicer and a first multiplexer, a first path multiplexer output, and a second DFE path including a second path input configured to receive a second communication symbol, a second adder, a second DFE filter, a second slicer, and a second multiplexer.

公开(公告)号：US11855812B2

公开(公告)日：2023-12-26

申请号：US17736802

申请日：2022-05-04

申请人： Micron Technology, Inc.

发明人： Jennifer E. Taylor ,  Won Joo Yun

IPC分类号： H04L25/03

CPC分类号： H04L25/03057

摘要： A keeper device is used in a hybrid loop unrolled DFE circuit to selectively output signals from equalizers corresponding to a specific possibility of the values of the previous bit (e.g., logical high or logical low) when DFE technique is not used. Those equalizers corresponding to possibilities other than the specific possibility of the values of the previous bit are disabled in the hybrid loop unrolled DFE circuit. As such, the hybrid loop unrolled DFE circuit saves power when the DFE technique is not used since only a portion of the total equalizers in the hybrid loop unrolled DFE circuit are powered.

公开(公告)号：US20230362041A1

公开(公告)日：2023-11-09

申请号：US18142977

申请日：2023-05-03

申请人： Rambus Inc.

发明人： Ehud Nir

IPC分类号： H04L25/03 ,  H04L27/06

CPC分类号： H04L25/03057 ,  H04L27/06 ,  H04L25/4917

摘要： Technologies for signaling compression inside a partially unrolled decision feedback equalizer (DFE) are described. The signaling compression associated with partially unrolled DFE results in multiplexers selecting a 1-bit output value from one of two 1-bit input values, which are decoding the actual multi-bit candidate levels and transforming the selected 1-bit output value to a multi-bit sliced value by adding to it a pointer value of a pulse-amplitude modulation (PAM) level. The signaling compression reduces the power and area of an N-tap DFE, where N is a positive integer.