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公开(公告)号：US20250038641A1
公开(公告)日：2025-01-30
申请号：US18764852
申请日：2024-07-05
Applicant: MEDIATEK INC.
Inventor： Chung-Wei HSU , Wei-Hsin TSENG
Abstract: A voltage regulator with diode retention is shown, which includes an input terminal receiving a supply voltage, an output terminal providing a regulated voltage, and a main circuit coupled between the input terminal and the output terminal. In a normal mode, the main circuit transforms the supply voltage to a first voltage as the regulated voltage. In a sleep mode, the voltage regulator provides a diode connected between the input terminal and the output terminal of the voltage regulator, to generate a second voltage as the regulated voltage. The second voltage is lower than the first voltage.
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