公开(公告)号：US20230378971A1

公开(公告)日：2023-11-23

申请号：US18157150

申请日：2023-01-20

Applicant: MEDIATEK INC.

Inventor： Pang-Yen CHIN ,  Wei-Hsin TSENG ,  Kuan-Ta CHEN

IPC: H03M1/46

CPC classification number: H03M1/46

Abstract: A high-speed successive-approximation register analog-to-digital converter (SAR ADC) is shown. A digital-to-analog converter (DAC), a comparator, and a SAR logic circuit are configured to form a loop for successive approximation of a digital representation of an analog input. The SAR logic circuit includes a plurality of latches. Each latch uses a one-gate-delay circuit to wire the comparator to one bit-control terminal of the DAC.

公开(公告)号：US20240243736A1

公开(公告)日：2024-07-18

申请号：US18395917

申请日：2023-12-26

Applicant: MEDIATEK INC.

Inventor： Jhen-Kai WANG ,  Wei-Hsin TSENG

IPC: H03K5/01 ,  H03K17/687

CPC classification number: H03K5/01 ,  H03K17/6871

Abstract: A digital step attenuator (DSA) with efficient high-frequency signal attenuation is shown. The DSA has an attenuation circuit, a bypass switch, and a diversion circuit.
The attenuation circuit is coupled between an input node and an output node of the digital step attenuator. The bypass switch is controlled by a bypass control signal to provide a bypass path between the input node and the output node of the digital step attenuator. The diversion circuit couples a control terminal of the bypass switch to a ground terminal in response to the bypass control signal being in an inactive state.

公开(公告)号：US20250038641A1

公开(公告)日：2025-01-30

申请号：US18764852

申请日：2024-07-05

Applicant: MEDIATEK INC.

Inventor： Chung-Wei HSU ,  Wei-Hsin TSENG

IPC: H02M1/00 ,  H02M3/158

Abstract: A voltage regulator with diode retention is shown, which includes an input terminal receiving a supply voltage, an output terminal providing a regulated voltage, and a main circuit coupled between the input terminal and the output terminal. In a normal mode, the main circuit transforms the supply voltage to a first voltage as the regulated voltage. In a sleep mode, the voltage regulator provides a diode connected between the input terminal and the output terminal of the voltage regulator, to generate a second voltage as the regulated voltage. The second voltage is lower than the first voltage.

公开(公告)号：US20240243732A1

公开(公告)日：2024-07-18

申请号：US18395930

申请日：2023-12-26

Applicant: MEDIATEK INC.

Inventor： Wei-Hsin TSENG ,  Jhen-Kai WANG

IPC: H03H17/00 ,  H03H7/25 ,  H03H11/24

CPC classification number: H03H17/0054 ,  H03H7/25 ,  H03H11/24

Abstract: A multi-level digital step attenuator (DSA) with a hybrid attenuation circuit is shown. The hybrid attenuation circuit is coupled between an input node and an output node of the multi-level DSA. The bypass switch of the multi-level DSA is controlled to provide a bypass path between the input node and the output node of the of the multi-level DSA when the hybrid attenuation circuit is in a disabled state. In the first active state, the hybrid attenuation circuit is switched to form a T-type structure to provide a first amount of signal attenuation. In the second active state, the hybrid attenuation circuit is switched to form a Pi-type structure to provide a second amount of signal attenuation.

公开(公告)号：US20150263756A1

公开(公告)日：2015-09-17

申请号：US14576315

申请日：2014-12-19

Applicant: MediaTek Inc.

Inventor： Pao-Cheng CHIU ,  Wei-Hsin TSENG

IPC: H03M1/46 ,  H03M1/20 ,  H03M1/08

CPC classification number: H03M1/468 ,  H03M1/0607 ,  H03M1/08 ,  H03M1/1061

Abstract: Analog-to-digital-converters (ADC) are provided. The ADC contains a first capacitive digital-to-analog-converter (CDAC) and a control circuit. The CDAC, including n bit, is configured to connect a kth bit of the n bits to a first voltage reference to provide a first analog signal, convert the first analog signal into first digital code using 0th through (k−1)th bits that are less significant than the kth bit, connect the kth bit of the n bits to a second voltage reference to provide a second analog signal, and convert the second analog signal into second digital code using the 0th through (k−1)th bits that are less significant than the kth bit. The control circuit is configured to estimate a weight of the kth bit based on the first and second digital code.

Abstract translation: 提供模数转换器（ADC）。 ADC包含第一个电容数模转换器（CDAC）和一个控制电路。 包括n位的CDAC被配置为将n位的第k位连接到第一参考电压以提供第一模拟信号，使用第0到第（k-1）位将第一模拟信号转换为第一数字码， 比第k位更不重要，将n位的第k位连接到第二参考电压以提供第二模拟信号，并且使用第0到第（k-1）位将第二模拟信号转换为第二数字码， 不如第k位显着。 控制电路被配置为基于第一和第二数字码估计第k位的权重。