公开(公告)号：US20140269732A1

公开(公告)日：2014-09-18

申请号：US13845182

申请日：2013-03-18

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Zachy Haramaty ,  Ran Shani ,  Oded Wertheim

IPC: H04L12/741 ,  H04L12/713

CPC classification number: H04L12/465 ,  H04L12/4654 ,  H04L12/4658

Abstract: A method of communications at an encapsulating bridge includes receiving a packet having an unencapsulated-DA (destination address) and an associated encapsulation identifier. The unencapsulated-DA and the associated encapsulation identifier are used to determine a TxPort-unencapsulated network (unencapsulated network side transmit port) or an encapsulated-DA for the packet. This method reduces latency of processing by reducing lookups, thereby also increasing transmission bandwidth of the communications network. The invention also facilitates embodiments with reduced memory and processing requirements, as compared to conventional implementations. This method is particularly useful for MAC-in-MAC encapsulation.

Abstract translation: 在封装桥接器处的通信方法包括接收具有未封装的DA（目的地地址）和相关联的封装标识符的分组。 未封装的DA和相关联的封装标识符用于确定用于分组的TxPort未封装的网络（未封装的网络侧发送端口）或封装的DA。 该方法通过减少查找来减少处理的延迟，从而也增加通信网络的传输带宽。 与传统实现相比，本发明还有助于减少存储器和处理要求的实施例。 该方法对于MAC-in-MAC封装特别有用。

公开(公告)号：US20200371708A1

公开(公告)日：2020-11-26

申请号：US16416290

申请日：2019-05-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Karin Karmani ,  Lion Levi ,  Zachy Haramaty ,  Ran Shani

IPC: G06F3/06 ,  H04L12/861

Abstract: A network element including buffer address control circuitry for reading a given entry from a queue in a memory of a device external to the network element, the queue having at least a first entry and a last entry, the given entry including a destination address in the memory, output circuitry for writing data included in a packet received from external to the network element to the destination address in the memory in accordance with the given entry, and next entry assignment circuitry for assigning a next entry by: when the given entry is other than the last entry in the first queue, assigning the next entry to be an entry in the first queue after the given entry, and when the given entry is the last entry in the first queue, assigning the next entry to be the first entry in the first queue. Related apparatus and methods are also described.

公开(公告)号：US09667441B2

公开(公告)日：2017-05-30

申请号：US13845182

申请日：2013-03-18

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Zachy Haramaty ,  Ran Shani ,  Oded Wertheim

IPC: H04L12/46

CPC classification number: H04L12/465 ,  H04L12/4654 ,  H04L12/4658

Abstract: A method of communications at an encapsulating bridge includes receiving a packet having an unencapsulated-DA (destination address) and an associated encapsulation identifier. The unencapsulated-DA and the associated encapsulation identifier are used to determine a TxPort-unencapsulated network (unencapsulated network side transmit port) or an encapsulated-DA for the packet. This method reduces latency of processing by reducing lookups, thereby also increasing transmission bandwidth of the communications network. The invention also facilitates embodiments with reduced memory and processing requirements, as compared to conventional implementations. This method is particularly useful for MAC-in-MAC encapsulation.

公开(公告)号：US20140211808A1

公开(公告)日：2014-07-31

申请号：US13755137

申请日：2013-01-31

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Benny Koren ,  Carlos Nemerovsky ,  Ran Shani ,  Ido Bukspan

IPC: H04L12/24

CPC classification number: H04L41/00 ,  H04L41/046 ,  H04L49/30 ,  H04L49/356 ,  H04L67/26

Abstract: Communication apparatus includes a switch, which includes switching logic, multiple ports for connection to a network, and a management port, and which is configured to assign both a first link-layer address and a second link-layer address to the management port. A host processor includes a memory and a central processing unit (CPU), which is configured to run software implementing a management agent for managing functions of the switch. A network interface controller (NIC) is connected to the management port and is configured to convey incoming management packets, which are directed by the switch to the first link-layer address, to the CPU for processing by the management agent, and to write directly to the memory data contained in incoming remote direct memory access (RDMA) packets, which are directed by the switch to the second link-layer address.

Abstract translation: 通信装置包括交换机，其包括交换逻辑，用于连接到网络的多个端口和管理端口，并且被配置为向管理端口分配第一链路层地址和第二链路层地址。 主处理器包括存储器和中央处理单元（CPU），其被配置为运行实现用于管理交换机的功能的管理代理的软件。 网络接口控制器（NIC）连接到管理端口，并被配置为将由交换机引导的传入管理分组传送到第一链路层地址，以供管理代理处理，并直接写入 到由进入的远程直接存储器访问（RDMA）分组中包含的存储器数据，其由交换机指向第二链路层地址。

公开(公告)号：US08908704B2

公开(公告)日：2014-12-09

申请号：US13755137

申请日：2013-01-31

Applicant: Mellanox Technologies Ltd.

Inventor： Benny Koren ,  Carlos Nemerovsky ,  Ran Shani ,  Ido Bukspan

IPC: H04W4/00 ,  H04L12/24 ,  H04L12/931 ,  H04L12/935 ,  H04L29/08

CPC classification number: H04L41/00 ,  H04L41/046 ,  H04L49/30 ,  H04L49/356 ,  H04L67/26

Abstract: Communication apparatus includes a switch, which includes switching logic, multiple ports for connection to a network, and a management port, and which is configured to assign both a first link-layer address and a second link-layer address to the management port. A host processor includes a memory and a central processing unit (CPU), which is configured to run software implementing a management agent for managing functions of the switch. A network interface controller (NIC) is connected to the management port and is configured to convey incoming management packets, which are directed by the switch to the first link-layer address, to the CPU for processing by the management agent, and to write directly to the memory data contained in incoming remote direct memory access (RDMA) packets, which are directed by the switch to the second link-layer address.

Abstract translation: 通信装置包括交换机，其包括交换逻辑，用于连接到网络的多个端口和管理端口，并且被配置为向管理端口分配第一链路层地址和第二链路层地址。 主处理器包括存储器和中央处理单元（CPU），其被配置为运行实现用于管理交换机的功能的管理代理的软件。 网络接口控制器（NIC）连接到管理端口，并被配置为将由交换机引导的传入管理分组传送到第一链路层地址，以供管理代理处理，并直接写入 到由进入的远程直接存储器访问（RDMA）分组中包含的存储器数据，其由交换机指向第二链路层地址。