公开(公告)号：US10318238B2

公开(公告)日：2019-06-11

申请号：US16107867

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Brian Huber ,  Gary Howe

IPC: G06F5/06 ,  H03K5/26

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

公开(公告)号：US20180357041A1

公开(公告)日：2018-12-13

申请号：US16107867

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Brian Huber ,  Gary Howe

IPC: G06F5/06 ,  H03K5/26

CPC classification number: G06F5/06 ,  H03K5/26

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

公开(公告)号：US09778903B2

公开(公告)日：2017-10-03

申请号：US14573215

申请日：2014-12-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Brian Huber ,  Gary Howe

IPC: G06F5/06 ,  H03K5/26

CPC classification number: G06F5/06 ,  H03K5/26

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

公开(公告)号：US20170357482A1

公开(公告)日：2017-12-14

申请号：US15690085

申请日：2017-08-29

Applicant: Micron Technology, Inc.

Inventor： Brian Huber ,  Gary Howe

IPC: G06F5/06 ,  H03K5/26

CPC classification number: G06F5/06 ,  H03K5/26

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event in based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

公开(公告)号：US08988953B2

公开(公告)日：2015-03-24

申请号：US14016844

申请日：2013-09-03

Applicant: Micron Technology, Inc.

Inventor： Brian Huber

IPC: G11C7/00 ,  G11C8/18 ,  G11C7/10

CPC classification number: G11C8/18 ,  G11C7/10 ,  G11C7/1084

Abstract: Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals.

Abstract translation: 公开了在信号节点处提供和接收非数据信号的存储器和方法。 一个这样的存储器包括第一和第二信号节点以及第一和第二信号缓冲器。 第一信号缓冲器被配置为响应于第一数据选通信号而工作，并且还被配置为响应于非数据信号而工作。 第二信号缓冲器被配置为响应于第二数据选通信号而工作。 示例性的第一数据选通信号是由存储器提供的读数据选通信号。 在另一示例中，第一数据选通信号是由存储器接收的写数据选通信号。 非数据信号的示例包括数据屏蔽信号，数据有效信号，纠错信号以及其它信号。

公开(公告)号：US20140003163A1

公开(公告)日：2014-01-02

申请号：US14016844

申请日：2013-09-03

Applicant: Micron Technology, Inc.

Inventor： Brian Huber

IPC: G11C8/18 ,  G11C7/10

CPC classification number: G11C8/18 ,  G11C7/10 ,  G11C7/1084

Abstract: Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals.

Abstract translation: 公开了在信号节点处提供和接收非数据信号的存储器和方法。 一个这样的存储器包括第一和第二信号节点以及第一和第二信号缓冲器。 第一信号缓冲器被配置为响应于第一数据选通信号而工作，并且还被配置为响应于非数据信号而工作。 第二信号缓冲器被配置为响应于第二数据选通信号而工作。 示例性的第一数据选通信号是由存储器提供的读数据选通信号。 在另一示例中，第一数据选通信号是由存储器接收的写数据选通信号。 非数据信号的示例包括数据屏蔽信号，数据有效信号，纠错信号以及其它信号。

公开(公告)号：US08589641B2

公开(公告)日：2013-11-19

申请号：US13677771

申请日：2012-11-15

Applicant: Micron Technology, Inc.

Inventor： Brian Huber ,  Frank Ross ,  David R. Brown

IPC: G11C7/10

CPC classification number: G11C7/1063 ,  G11C7/1045 ,  G11C7/1051 ,  G11C11/4078

Abstract: Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command.

Abstract translation: 公开了诸如那些涉及固态存储器件的方法和装置，该固态存储器件包括配置成以组合的并行和串行读取方案读取的状态寄存器。 一种这样的固态存储器包括状态寄存器，其被配置为存储指示存储器的状态信息的多个位。 在存储器件中提供状态信息的一种这样的方法包括以并行形式提供存储器件的状态信息。 该方法还包括响应于接收至少一个读取命令以并行形式提供状态信息之后以串行形式提供状态信息。

公开(公告)号：US10120647B2

公开(公告)日：2018-11-06

申请号：US15690085

申请日：2017-08-29

Applicant: Micron Technology, Inc.

Inventor： Brian Huber ,  Gary Howe

IPC: G06F5/06 ,  H03K5/26

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event in based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

公开(公告)号：US20130073803A1

公开(公告)日：2013-03-21

申请号：US13677771

申请日：2012-11-15

Applicant: Micron Technology, Inc.

Inventor： Brian Huber ,  Frank Ross ,  David R. Brown

IPC: G06F12/00

CPC classification number: G11C7/1063 ,  G11C7/1045 ,  G11C7/1051 ,  G11C11/4078

Abstract: Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command.