公开(公告)号：US12118232B2

公开(公告)日：2024-10-15

申请号：US17622365

申请日：2020-11-05

Applicant: Anhui Cambricon Information Technology Co., Ltd.

Inventor： Junwei Zhang ,  Jingye Xuan ,  Shangbin Chen

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F3/0655 ,  G06F3/0673 ,  G11C7/1045 ,  G11C7/1084 ,  G11C7/1063

Abstract: A memory is included in a combined processing apparatus which may include a computing device, a general interconnection interface, and another processing device. The computing device interacts with the other processing device to jointly complete a computing operation specified by a user. A storage device is respectively connected to the computing device and the other processing device, and is configured to store data of the computing device and the other processing device. The solution of the present disclosure can be widely applied to various data storage fields.

公开(公告)号：US12106821B2

公开(公告)日：2024-10-01

申请号：US17439742

申请日：2021-07-08

Applicant: ChangXin Memory Technologies, Inc.

Inventor： Enpeng Gao ,  Kangling Ji ,  Zengquan Wu

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/1066 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222

Abstract: This application relates to a data transmission circuit, a method making it, and a storage device. The circuit includes a mode register data storage unit and an array area data storage unit. The mode register data storage unit outputs mode register data in response to a first clock signal; the output terminal of the array area data storage unit and the output terminal of the mode register data storage unit are both connected to the first node, the array area data storage unit receives array area data in response to the first pointer signal, and outputs the array area data in response to the second pointer signal. This technic can accurately control the mode register data and the array area data to output through the respective output channels in turn.

公开(公告)号：US12100475B2

公开(公告)日：2024-09-24

申请号：US18496693

申请日：2023-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjin Kim ,  Jungsik Park ,  Soongmann Shin

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18

CPC classification number: G11C7/222 ,  G11C7/1045 ,  G11C7/1063 ,  G11C7/109 ,  G11C8/18

Abstract: In an apparatus, a memory controller, a memory device, and a method for switching frequencies of clock signals to reduce power consumption, when the memory device performs an internal operation according to a command of the memory controller, a frequency of a clock signal of the memory controller is changed. The memory controller switches the frequency of the clock signal to a low frequency according to assertion of a status signal that indicates a busy operation status of the memory device according to the command, and switches the frequency of the clock signal to a high frequency according to de-assertion of the status signal that indicates a ready operation status of the memory device.

公开(公告)号：US20240265953A1

公开(公告)日：2024-08-08

申请号：US18581694

申请日：2024-02-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/10

CPC classification number: G11C7/1012 ,  G11C7/1045 ,  G11C7/1087 ,  G11C2207/105

Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.

公开(公告)号：US12057185B2

公开(公告)日：2024-08-06

申请号：US18083992

申请日：2022-12-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Xiangang Luo ,  Peter Feeley ,  Devin M. Batutis ,  Jiangang Wu ,  Sampath K. Ratnam ,  Shane Nowell ,  Karl D. Schuh

IPC: G11C29/00 ,  G06F12/02 ,  G11C7/10 ,  G11C16/26 ,  G11C29/02 ,  G11C29/50

CPC classification number: G11C29/50 ,  G06F12/0246 ,  G11C7/1045 ,  G11C16/26 ,  G11C29/022

Abstract: A method includes initiating a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin, measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin, determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets, and in response to determining that the value is less than the current value, designating the second bin as the current bin.

公开(公告)号：US20240242756A1

公开(公告)日：2024-07-18

申请号：US18618777

申请日：2024-03-27

Applicant: LONGITUDE LICENSING LIMITED

Inventor： Chikara Kondo

IPC: G11C11/4093 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F13/161 ,  G11C7/1045 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/00

Abstract: A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.

公开(公告)号：US12009021B2

公开(公告)日：2024-06-11

申请号：US17682526

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Lien Linus Lu

IPC: G11C11/22 ,  G11C7/10

CPC classification number: G11C11/2255 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297

Abstract: A system for processing a data array, such as transposing a matrix, includes a two-dimensional array of memory cells, such as FeFETs, each having an input end, an output end and a control end. The system also includes an input interface is adapted to supply signals indicative of a subset of the data array, such as a row of a matrix, and output control signals to the input ends of a selected column of the memory cells. The system further includes an output interface adapted to receive the data stored in the memory array from the output ends of a selected row of the memory cells. A method of processing a data array, such as transposing a matrix, include writing subsets of the data array to the memory array column-by-column, and reading from the memory cells, row-by-row.

公开(公告)号：US12007916B2

公开(公告)日：2024-06-11

申请号：US18295143

申请日：2023-04-03

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F13/16 ,  G06F12/02 ,  G06F12/06 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22

CPC classification number: G06F13/1694 ,  G06F12/0246 ,  G06F12/0623 ,  G06F12/0646 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/20 ,  G11C7/22 ,  G06F13/1678 ,  G06F2212/7206

Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

公开(公告)号：US11955198B2

公开(公告)日：2024-04-09

申请号：US18097459

申请日：2023-01-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/10

CPC classification number: G11C7/1012 ,  G11C7/1045 ,  G11C7/1087 ,  G11C2207/105

Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.

公开(公告)号：US11914874B2

公开(公告)日：2024-02-27

申请号：US17392085

申请日：2021-08-02

Applicant: Lodestar Licensing Group LLC

Inventor： Dean D. Gans ,  Yoshiro Riho ,  Shunichi Saito ,  Osamu Nagashima

IPC: G06F3/00 ,  G06F3/06 ,  G11C7/10 ,  G06F13/16

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0673 ,  G06F13/16 ,  G11C7/1045 ,  G11C2207/2272

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.