公开(公告)号：US10922098B2

公开(公告)日：2021-02-16

申请号：US15726305

申请日：2017-10-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gregory Edvenson ,  Jeremy Chritz ,  David Hulton

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/448 ,  G06F8/30 ,  G06F9/445

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.

公开(公告)号：US20190108019A1

公开(公告)日：2019-04-11

申请号：US16116869

申请日：2018-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gregory Edvenson ,  David Hulton ,  Jeremy Chritz

IPC: G06F9/30 ,  G06N20/00

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.

公开(公告)号：US11669344B2

公开(公告)日：2023-06-06

申请号：US16117529

申请日：2018-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gregory Edvenson ,  Jeremy Chritz ,  David Hulton

IPC: G06F15/80 ,  G06F9/448 ,  G06F9/30 ,  G06F8/30 ,  G06F9/445

CPC classification number: G06F9/4496 ,  G06F8/31 ,  G06F9/30007 ,  G06F9/30109 ,  G06F9/44505 ,  G06F15/80

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.

公开(公告)号：US11061674B2

公开(公告)日：2021-07-13

申请号：US15726293

申请日：2017-10-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gregory Edvenson ,  David Hulton ,  Jeremy Chritz

IPC: G06F9/38 ,  G06F15/78 ,  G06F15/80 ,  G06F9/30 ,  G06N20/00

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.

公开(公告)号：US11003448B2

公开(公告)日：2021-05-11

申请号：US16116869

申请日：2018-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gregory Edvenson ,  David Hulton ,  Jeremy Chritz

IPC: G06F15/76 ,  G06F15/80 ,  G06F9/30 ,  G06N20/00 ,  G06F15/78 ,  G06F9/38

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.

公开(公告)号：US20190108018A1

公开(公告)日：2019-04-11

申请号：US15726293

申请日：2017-10-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gregory Edvenson ,  David Hulton ,  Jeremy Chritz

IPC: G06F9/30 ,  G06F15/18

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.