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公开(公告)号：US20050083718A1
公开(公告)日：2005-04-21
申请号：US10690368
申请日：2003-10-21
Applicant: Mark Lysinger
Inventor： Mark Lysinger
Abstract: A method and apparatus for comparing a stored data word to a comparison data word in a magnitude content addressable memory (MCAM) are disclosed. Each cell of the MCAM includes a data memory cell for storing a data value and a magnitude comparator, coupled to the first memory cell. The magnitude comparator receives the data value and a comparison value as inputs, and produces two magnitude signals as outputs. The first magnitude signal indicates whether the comparison value is greater than the data value and the second magnitude signal indicates whether the comparison value is less than the data value. The magnitude comparator also receives magnitude signals from the preceding MCAM cell. The previous magnitude signals are output as the first and second magnitude signals when the data value and the comparison value are equal. The MCAM enables data words of arbitrary length to be compared with comparison words. The MCAM cell may contain a second memory for storing a mask value. When the mask value is set, the MCAM cell operates as if the comparison and data values were equal.
Abstract translation: 公开了一种用于将存储的数据字与幅度内容可寻址存储器（MCAM）中的比较数据字进行比较的方法和装置。 MCAM的每个单元包括用于存储数据值的数据存储单元和耦合到第一存储单元的幅度比较器。 幅度比较器接收数据值和比较值作为输入，并产生两个幅度信号作为输出。 第一幅度信号指示比较值是否大于数据值，第二幅度信号指示比较值是否小于数据值。 幅度比较器还从前面的MCAM单元接收幅度信号。 当数据值和比较值相等时，先前的幅度信号作为第一和第二幅度信号输出。 MCAM使任意长度的数据字与比较字进行比较。 MCAM单元可以包含用于存储掩码值的第二存储器。 当设置掩码值时，MCAM单元就像比较和数据值相等一样工作。
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公开(公告)号：US07336517B2
公开(公告)日：2008-02-26
申请号：US11746259
申请日：2007-05-09
Applicant: Mark Lysinger
Inventor： Mark Lysinger
Abstract: A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority encoder is operatively connected to the array of CAM cells and determines a highest priority matching address for data within the array of CAM cells. The priority encoder includes match lines associated with respective rows and precharged bus lines connected into respective match lines that are discharged whenever there is a match signal such that the highest precharged bus line discharged results in an encoded address.
Abstract translation: 优先编码器可以用于通常具有排列成列和行的CAM单元阵列的内容寻址存储器（CAM）设备，每个行具有指示比较数据具有相应行内的匹配数据的匹配信号。 优先编码器可操作地连接到CAM单元阵列，并确定CAM单元阵列内的数据的最高优先级匹配地址。 优先编码器包括与相应行相关联的匹配线和连接到相应匹配线中的预充电总线，每当匹配信号被放电时，放电的最高预充电总线导致编码地址。
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公开(公告)号：US07196922B2
公开(公告)日：2007-03-27
申请号：US11188396
申请日：2005-07-25
Applicant: Mark Lysinger
Inventor： Mark Lysinger
CPC classification number: G11C15/04
Abstract: A programmable priority encoder is disclosed for use with the device such as a Content Addressable Memory (CAM) device having a plurality of array objects to be encoded in binary and arranged in row and columns. Match lines are adapted to be connected to a plurality of arrayed objects associated with respective rows. A plurality of encoder cells, each having a memory element and forming an encoder block are arranged in rows. Precharged bus lines are operative with the encoder cells and match lines. The precharged bus lines are discharged indicating a match and priority is assigned to rows based on logic values stored within the memory elements of the encoder cell.
Abstract translation: 公开了一种可编程优先编码器，用于与诸如内容可寻址存储器（CAM）装置的装置一起使用，该装置具有要以二进制编码并以行和列排列的多个阵列对象。 匹配线适于连接到与相应行相关联的多个阵列对象。 多个具有存储元件并形成编码器块的编码器单元被排列成行。 预充电总线与编码器单元和匹配线一起工作。 预充电的总线线路被排出，指示匹配，并且基于存储在编码器单元的存储器元件内的逻辑值将优先级分配给行。
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Patent Agency Ranking
4.发明授权公开(公告)号：US07233512B2
公开(公告)日：2007-06-19
申请号：US11048224
申请日：2005-02-01
Applicant: Mark Lysinger , Francois Jacquet , Phillippe Roche
Inventor： Mark Lysinger , Francois Jacquet , Phillippe Roche
IPC: G11C15/00
Abstract: A Content Addressable Memory (CAM) circuit includes memory cells preferably formed as two memory cells each having internal nodes. A compare circuit is operative with the memory cells. A common terminal (VPL) exists for the memory cells. Capacitors are added between the internal nodes of each of the memory cells and common terminal for memory cell stability.
Abstract translation: 内容可寻址存储器（CAM）电路包括优选地形成为具有内部节点的两个存储器单元的存储器单元。 比较电路与存储器单元一起工作。 存储单元存在公共端（VPL）。 在每个存储单元的内部节点和公共端子之间添加电容器用于存储器单元的稳定性。
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公开(公告)号：US07218542B2
公开(公告)日：2007-05-15
申请号：US11134890
申请日：2005-05-23
Applicant: Mark Lysinger
Inventor： Mark Lysinger
Abstract: A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority encoder is operatively connected to the array of CAM cells and determines a highest priority matching address for data within the array of CAM cells. The priority encoder includes match lines associated with respective rows and precharged bus lines connected into respective match lines that are discharged whenever there is a match signal such that the highest precharged bus line discharged results in an encoded address.
Abstract translation: 优先编码器可以用于通常具有排列成列和行的CAM单元阵列的内容寻址存储器（CAM）设备，每个行具有指示比较数据具有相应行内的匹配数据的匹配信号。 优先编码器可操作地连接到CAM单元阵列，并确定CAM单元阵列内的数据的最高优先级匹配地址。 优先编码器包括与相应行相关联的匹配线和连接到相应匹配线中的预充电总线，每当匹配信号被放电时，放电的最高预充电总线导致编码地址。
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公开(公告)号：US20070019455A1
公开(公告)日：2007-01-25
申请号：US11188396
申请日：2005-07-25
Applicant: Mark Lysinger
Inventor： Mark Lysinger
IPC: G11C15/00
CPC classification number: G11C15/04
Abstract: A programmable priority encoder is disclosed for use with the device such as a Content Addressable Memory (CAM) device having a plurality of array objects to be encoded in binary and arranged in row and columns. Match lines are adapted to be connected to a plurality of arrayed objects associated with respective rows. A plurality of encoder cells, each having a memory element and forming an encoder block are arranged in rows. Precharged bus lines are operative with the encoder cells and match lines. The precharged bus lines are discharged indicating a match and priority is assigned to rows based on logic values stored within the memory elements of the encoder cell.
Abstract translation: 公开了一种可编程优先编码器，用于与诸如内容可寻址存储器（CAM）装置的装置一起使用，该装置具有要以二进制编码并以行和列排列的多个阵列对象。 匹配线适于连接到与相应行相关联的多个阵列对象。 多个具有存储元件并形成编码器块的编码器单元被排列成行。 预充电总线与编码器单元和匹配线一起工作。 预充电的总线线路被排出，指示匹配，并且基于存储在编码器单元的存储器元件内的逻辑值将优先级分配给行。
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公开(公告)号：US20060262582A1
公开(公告)日：2006-11-23
申请号：US11134890
申请日：2005-05-23
Applicant: Mark Lysinger
Inventor： Mark Lysinger
IPC: G11C15/00
Abstract: A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority encoder is operatively connected to the array of CAM cells and determines a highest priority matching address for data within the array of CAM cells. The priority encoder includes match lines associated with respective rows and precharged bus lines connected into respective match lines that are discharged whenever there is a match signal such that the highest precharged bus line discharged results in an encoded address.
Abstract translation: 优先编码器可以用于通常具有排列成列和行的CAM单元阵列的内容寻址存储器（CAM）设备，每个行具有指示比较数据具有相应行内的匹配数据的匹配信号。 优先编码器可操作地连接到CAM单元阵列，并确定CAM单元阵列内的数据的最高优先级匹配地址。 优先编码器包括与相应行相关联的匹配线和连接到相应匹配线中的预充电总线，每当匹配信号被放电时，放电的最高预充电总线导致编码地址。
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8.发明申请公开(公告)号：US20060171183A1
公开(公告)日：2006-08-03
申请号：US11048224
申请日：2005-02-01
Applicant: Mark Lysinger , Francois Jacquet , Phillippe Roche
Inventor： Mark Lysinger , Francois Jacquet , Phillippe Roche
IPC: G11C15/00
Abstract: A Content Addressable Memory (CAM) circuit includes memory cells preferably formed as two memory cells each having internal nodes. A compare circuit is operative with the memory cells. A common terminal (VPL) exists for the memory cells. Capacitors are added between the internal nodes of each of the memory cells and common terminal for memory cell stability.
Abstract translation: 内容可寻址存储器（CAM）电路包括优选地形成为具有内部节点的两个存储器单元的存储器单元。 比较电路与存储器单元一起工作。 存储单元存在公共端（VPL）。 在每个存储单元的内部节点和公共端子之间添加电容器用于存储器单元的稳定性。
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