公开(公告)号：US07929655B2

公开(公告)日：2011-04-19

申请号：US12481375

申请日：2009-06-09

Applicant: Matthew Peter Hutson

Inventor： Matthew Peter Hutson

IPC: H04L25/38 ,  H04L7/00

CPC classification number: H04L7/02

Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.

Abstract translation: 一种用于控制第一时钟域中的信号序列向多个其它时钟域的传送的系统。 该系统包括：检测电路，用于检测来自时钟域的信号的接收，并且当从时钟域接收的所有信号具有共同的状态时，设置更新信号; 以及用于接收更新信号的选通电路，并且当更新信号被设置时可操作以允许序列中的下一个信号在第一电路的输入处被接收。

公开(公告)号：US20090316845A1

公开(公告)日：2009-12-24

申请号：US12481375

申请日：2009-06-09

Applicant: Matthew Peter Hutson

Inventor： Matthew Peter Hutson

IPC: H04L7/00

CPC classification number: H04L7/02

Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.

Abstract translation: 一种用于控制第一时钟域中的信号序列向多个其它时钟域的传送的系统。 该系统包括：检测电路，用于检测来自时钟域的信号的接收，并且当从时钟域接收的所有信号具有共同的状态时，设置更新信号; 以及用于接收更新信号的选通电路，并且当更新信号被设置时可操作以允许序列中的下一个信号在第一电路的输入处被接收。

公开(公告)号：US07545896B2

公开(公告)日：2009-06-09

申请号：US11137105

申请日：2005-05-24

Applicant: Matthew Peter Hutson

Inventor： Matthew Peter Hutson

IPC: H04L7/00

CPC classification number: H04L7/02

Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.

Abstract translation: 一种用于控制第一时钟域中的信号序列向多个其它时钟域的传送的系统。 该系统包括：检测电路，用于检测来自时钟域的信号的接收，并且当从时钟域接收的所有信号具有共同的状态时，设置更新信号; 以及用于接收更新信号的选通电路，并且当更新信号被设置时可操作以允许序列中的下一个信号在第一电路的输入处被接收。