HARDWARE DISTRIBUTED ARCHITECTURE IN A DATA TRANSFORM ACCELERATOR

    公开(公告)号:US20240119022A1

    公开(公告)日:2024-04-11

    申请号:US18484443

    申请日:2023-10-10

    CPC classification number: G06F13/4282

    Abstract: A method includes obtaining data to process using at least one data transform operation. The method further includes determining a processing path for the data to traverse at least a first data transform engine and a second data transform engine. The method also includes directing the data to the first data transform engine. The first data transform engine is to perform a first data transform operation on the data. The method further includes directing the data to the second data transform engine, the second data transform engine to perform a second data transform operation on the data.

    HARDWARE DISTRIBUTED ARCHITECTURE
    2.
    发明公开

    公开(公告)号:US20240121185A1

    公开(公告)日:2024-04-11

    申请号:US18484428

    申请日:2023-10-10

    CPC classification number: H04L45/566 H04L45/42

    Abstract: A network processing system includes an interface connection to obtain a packet. The network processing system also includes one or more packet processing components individually connected to a system communication channel. The one or more packet processing components are individually configured to perform a packet processing operation to the packet. The network processing system also includes a queueing system connected to the system communication channel. The queueing system determines a processing path of the packet from the interface connection and through the one or more packet processing components. The one or more packet processing components are individually configured to direct the packet to a next component using the processing path.

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