公开(公告)号：US20220165330A1

公开(公告)日：2022-05-26

申请号：US17543547

申请日：2021-12-06

Applicant: MediaTek Inc.

Inventor： Tun-Fei Chien ,  Chia-Wei Wang

IPC: G11C11/418 ,  G11C11/419

Abstract: Examples pertaining to double-pitch layout techniques in designing a memory circuit layout are described. In a memory circuit, a layout of a first column of M×1 one-bit memory cells of an array of memory cells and a layout of a second column of M×1 one-bit memory cells of the array of memory cells are mirrored in horizontal and vertical axes such that a first group of input/output (I/O) pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of a layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array.

公开(公告)号：US11222691B2

公开(公告)日：2022-01-11

申请号：US16813723

申请日：2020-03-09

Applicant: MediaTek Inc.

Inventor： Tun-Fei Chien ,  Chia-Wei Wang

IPC: G11C11/4093 ,  G11C11/418 ,  G11C11/419

Abstract: Examples pertaining to double-pitch layout techniques in designing a memory circuit layout are described. In a memory circuit, a layout of a first column of M×1 one-bit memory cells of an array of memory cells and a layout of a second column of M×1 one-bit memory cells of the array of memory cells are mirrored in horizontal and vertical axes such that a first group of input/output (I/O) pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of a layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array.

公开(公告)号：US20210280237A1

公开(公告)日：2021-09-09

申请号：US16813723

申请日：2020-03-09

Applicant: MediaTek Inc.

Inventor： Tun-Fei Chien ,  Chia-Wei Wang

IPC: G11C11/418 ,  G11C11/419

Abstract: Examples pertaining to double-pitch layout techniques in designing a memory circuit layout are described. In a memory circuit, a layout of a first column of M×1 one-bit memory cells of an array of memory cells and a layout of a second column of M×1 one-bit memory cells of the array of memory cells are mirrored in horizontal and vertical axes such that a first group of input/output (I/O) pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of a layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array.