公开(公告)号：US20180181683A1

公开(公告)日：2018-06-28

申请号：US15387958

申请日：2016-12-22

Applicant: Mellanox Technologies, Ltd.

Inventor： Roy ARMONI ,  Or DAVIDI

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5022

Abstract: A method, computer program, and apparatus are described for finding the logical equivalence between register transfer level (RTL) wires and post synthesis nets in a netlist. In some example embodiments, the method includes minimizing nets in a netlist and matching each RTL wire to a netlist net. In some example embodiments, the method also includes determining if an RTL wire is logically equivalent to a netlist net. In some example embodiments, the method also includes determining a new candidate for a net if the RTL wire and associated netlist net are not logically equivalent.

公开(公告)号：US20190318056A1

公开(公告)日：2019-10-17

申请号：US15953964

申请日：2018-04-16

Applicant: Mellanox Technologies, Ltd.

Inventor： Yael MELLER ,  Or DAVIDI ,  Roy ARMONI

IPC: G06F17/50

Abstract: Embodiments are disclosed for solving a Boolean formula generated from an input design using an iterative loop using a computer-implemented Boolean satisfiability solver. An example method includes accessing data qualifier signals indicating one or more variables in a Boolean formula. The example method further includes marking the one or more variables in the Boolean formula as data qualifier variables based on the respective data qualifier signals. The example method further includes instructing a computer implemented Boolean satisfiability solver to solve the Boolean formula using an iterative loop, where operation of the iterative loop is prioritized based on the data qualifier variables. Corresponding apparatuses and non-transitory computer readable storage media are also provided.