公开(公告)号：US20220342668A1

公开(公告)日：2022-10-27

申请号：US17468574

申请日：2021-09-07

Applicant: Microchip Technology Inc.

Inventor： Christopher I. W. NORRIE

IPC: G06F9/30 ,  G06F9/38

Abstract: In one implementation devoid of an effective address generator a method of call operation comprises pushing one or more parameters onto a first stack, pushing the contents of one or more registers onto a second stack, popping off the first stack one or more of the parameters into one or more of the registers whose contents were pushed onto the second stack, performing register to register operations on the one or more registers whose contents were pushed onto the second stack with a result of the register to register operations being stored in a result register, the result register being one of the one or more registers whose contents were pushed onto the second stack, popping off the second stack the contents of all the one or more registers into their respective registers from which they came, and returning control to an instruction following the call.

公开(公告)号：US20220342844A1

公开(公告)日：2022-10-27

申请号：US17701582

申请日：2022-03-22

Applicant: Microchip Technology Inc.

Inventor： Christopher I. W. NORRIE

IPC: G06F15/80

Abstract: In one implementation a vector processor unit having preload registers for at least some of vector length, vector constant, vector address, and vector stride. Each preload register has an input and an output. All the preload register inputs are coupled to receive a new vector parameters. Each of the preload registers' outputs are coupled to a first input of a respective multiplexor, and the second input of all the respective multiplexors are coupled to the new vector parameters.

公开(公告)号：US20240394062A1

公开(公告)日：2024-11-28

申请号：US18534203

申请日：2023-12-08

Applicant: Microchip Technology Inc.

Inventor： Christopher I. W. NORRIE

IPC: G06F9/38 ,  G06F9/30

Abstract: In one implementation a processor has an instruction fetch circuit fetching instructions, the instruction fetch circuit having an input and an output and a decode circuit to decode the fetched instructions, the decode circuit having a first and second input, and an output, wherein the decode circuit first input is coupled to the instruction fetch circuit output receiving the fetched instructions, and an execution circuit executing the decoded fetched instructions, the execution circuit having an input coupled to the decode circuit output to receive the decoded fetched instructions, and a switch instruction circuit (SIC) to detect and execute switch instructions of the fetched instructions, the SIC having an input and an output, wherein the SIC input is coupled to the instruction fetch circuit output to receive the fetched instructions, wherein the SIC output is coupled to the decode circuit second input and the instruction fetch circuit input.

公开(公告)号：US20250060901A1

公开(公告)日：2025-02-20

申请号：US18938806

申请日：2024-11-06

Applicant: Microchip Technology Inc.

Inventor： Christopher I. W. NORRIE

IPC: G06F3/06

Abstract: A method for gather/scatter operations in a vector processor includes: (a) checking for a read port start signal and when received setting an increment count to zero; (b) initiating a memory read using a port's address register, and setting the increment count to increment count+1; (c) incrementing the port's address register by a port's stride register; (d) checking to see if the increment count is greater than or equal to a port's length register and when not so proceeding to (b); and (e) checking to see if the increment count is greater than or equal to a port's length register and when so proceeding to (a).

公开(公告)号：US20220342590A1

公开(公告)日：2022-10-27

申请号：US17669995

申请日：2022-02-11

Applicant: Microchip Technology Inc.

Inventor： Christopher I. W. NORRIE

IPC: G06F3/06

Abstract: In one implementation a vector processor gather/scatter apparatus comprises a plurality of vector ports, and a random access memory, where the plurality of vector ports are in communication with the random access memory, and where one or more of the plurality of vector ports uses one or more of an address register and one or more of a stride register in communication with the random access memory to allow the gather/scatter of random access memory contents.