公开(公告)号：US11017135B2

公开(公告)日：2021-05-25

申请号：US15667363

申请日：2017-08-02

Applicant: Microchip Technology Incorporated

Inventor： Athmanathan Vaidyanathan

IPC: G01R31/28 ,  G06F30/30 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3185

Abstract: Embodiments of the present disclosure may include a system for scanning a circuit, the embodiments including flip-flops, latches interleaved between the flip-flops, multiplexers configured to propagate scan data between the flip-flops and latches, and scan logic configured to control the multiplexers to load test data into the flip-flops and latches. A first pair of latches are interleaved between a first pair of flip-flops.

公开(公告)号：US20170329884A1

公开(公告)日：2017-11-16

申请号：US15667363

申请日：2017-08-02

Applicant: Microchip Technology Incorporated

Inventor： Athmanathan Vaidyanathan

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G06F17/5045 ,  G01R31/31704 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318544 ,  G01R31/318558

Abstract: Embodiments of the present disclosure may include a system for scanning a circuit, the embodiments including flip-flops, latches interleaved between the flip-flops, multiplexers configured to propagate scan data between the flip-flops and latches, and scan logic configured to control the multiplexers to load test data into the flip-flops and latches. A first pair of latches are interleaved between a first pair of flip-flops.

公开(公告)号：US20170146600A1

公开(公告)日：2017-05-25

申请号：US15359692

申请日：2016-11-23

Applicant: Microchip Technology Incorporated

Inventor： Athmanathan Vaidyanathan ,  Eric Schroeder

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31723 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318544 ,  G01R31/318558

Abstract: A system for scanning a circuit includes flip-flops and latches includes a multiplexer to couple an output of a flip-flop with an input of a latch. The multiplexer has an input receiving an input signal for the latch and another input coupled with output of the flip-flop. The system further another multiplexer to couple output of the first multiplexer with an input of another flip-flop. The system also includes scan logic for controlling multiplexers to load test data into the flip-flop and into the latch from the flip-flop. The system also includes scan logic for passing output of the flip-flop and the latch into portions of the circuit to be tested.