公开(公告)号：US20250112035A1

公开(公告)日：2025-04-03

申请号：US18401902

申请日：2024-01-02

Applicant: Microchip Technology Incorporated

Inventor： Steve Nagel ,  Bomy Chen ,  Bruce Odekirk ,  Pejman Khosropour ,  Robin Liu ,  Andy Tu ,  Thomas Krutsick

IPC: H01L21/02 ,  H01L29/04 ,  H01L29/16 ,  H01L29/20

Abstract: A method includes performing a pressing operation on a volume of silicon carbide (SiC) powder to form a polycrystalline SiC (poly-SiC) ingot, and divide the poly-SiC ingot into a plurality of poly-SiC wafer bases. The method further includes, for a respective poly-SiC wafer base, bonding a silicon (Si) wafer structure to the respective poly-SiC wafer base to define a hybrid Si/poly-SiC stack structure, and performing a dividing process to remove a partial thickness of the Si wafer structure from the hybrid Si/poly-SiC stack structure to provide a hybrid Si/poly-SiC wafer comprising a remaining portion of the Si wafer structure bonded to the respective poly-SiC wafer base.

公开(公告)号：US20240321760A1

公开(公告)日：2024-09-26

申请号：US18369310

申请日：2023-09-18

Applicant: Microchip Technology Incorporated

Inventor： Steve Nagel ,  Bomy Chen

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L23/5383 ,  H01L25/0655

Abstract: Interposers and methods for making interposers having a substrate having a surface defining a plane; a first portion of a metal line directly or indirectly supported by the substrate; a barrier layer on the first portion of the metal line; a second portion of the metal line on the first barrier layer, wherein the second portion is opposite the first portion across the barrier layer. The method includes etching a line pattern in a first portion of a metal layer through a first photoresist layer to form a first portion of a metal line, depositing a barrier layer on the first portion of the metal line, and etching a line pattern in a second portion of the metal layer through a second photoresist layer to form a second portion of a metal line wherein the second portion is opposite the first portion across the barrier layer.

公开(公告)号：US20240170325A1

公开(公告)日：2024-05-23

申请号：US18200688

申请日：2023-05-23

Applicant: Microchip Technology Incorporated

Inventor： Steve Nagel ,  Bomy Chen

IPC: H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76251 ,  H01L27/1203

Abstract: Methods for preparing a donor silicon wafer by applying a SiGe layer on a silicon substrate wafer, depositing a silicon layer on the SiGe layer, etching the silicon layer to form an opening in the silicon layer, wet etching the SiGe layer through the opening in the silicon layer to partially remove SiGe material from the SiGe layer and preserve the silicon layer, depositing a buried oxide layer on the silicon layer, etching the buried oxide layer to form a body bias area, and depositing silicon in the body bias area; bonding a recipient handle wafer to the etched buried oxide layer of the donor silicon wafer to define a BOX; and wet etching the SiGe layer to release the donor silicon wafer from the recipient handle wafer.