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公开(公告)号：US20240036977A1
公开(公告)日：2024-02-01
申请号：US17874952
申请日：2022-07-27
Applicant: Micron Technology, Inc.
Inventor： Luca Porzio , Ferdinando Pascale , Roberto Izzi , Marco Onorato , Erminio Di Martino
IPC: G06F11/14 , G06F1/24 , G06F9/4401
CPC classification number: G06F11/1417 , G06F1/24 , G06F9/4405
Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.
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公开(公告)号：US11983073B2
公开(公告)日：2024-05-14
申请号：US17874952
申请日：2022-07-27
Applicant: Micron Technology, Inc.
Inventor： Luca Porzio , Ferdinando Pascale , Roberto Izzi , Marco Onorato , Erminio Di Martino
IPC: G06F15/177 , G06F1/24 , G06F9/00 , G06F9/4401 , G06F11/14
CPC classification number: G06F11/1417 , G06F1/24 , G06F9/4405
Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.
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公开(公告)号：US20200152245A1
公开(公告)日：2020-05-14
申请号：US16731947
申请日：2019-12-31
Applicant: Micron Technology, Inc.
Inventor： Claudio Giaccio , Ferdinando Pascale , Erminio Di Martino , Raffaele Mastrangelo , Ferdinando D'Alessandro , Andrea Castaldo , Cristiano Castellano
Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.
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公开(公告)号：US10546620B2
公开(公告)日：2020-01-28
申请号：US16022351
申请日：2018-06-28
Applicant: Micron Technology, Inc.
Inventor： Claudio Giaccio , Ferdinando Pascale , Erminio Di Martino , Raffaele Mastrangelo , Ferdinando D'Alessandro , Andrea Castaldo , Cristiano Castellano
Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.
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公开(公告)号：US20240345925A1
公开(公告)日：2024-10-17
申请号：US18638245
申请日：2024-04-17
Applicant: Micron Technology, Inc.
Inventor： Luca Porzio , Ferdinando Pascale , Roberto Izzi , Marco Onorato , Erminio Di Martino
IPC: G06F11/14 , G06F1/24 , G06F9/4401
CPC classification number: G06F11/1417 , G06F1/24 , G06F9/4405
Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.
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Patent Agency Ranking
公开(公告)号：US11061431B2
公开(公告)日：2021-07-13
申请号：US16022307
申请日：2018-06-28
Applicant: Micron Technology, Inc.
Inventor： Claudio Giaccio , Ferdinando Pascale , Erminio Di Martino , Raffaele Mastrangelo , Ferdinando D'Alessandro , Andrea Castaldo , Cristiano Castellano
IPC: G06F1/12
Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.
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公开(公告)号：US11309055B2
公开(公告)日：2022-04-19
申请号：US16227021
申请日：2018-12-20
Applicant: Micron Technology, Inc.
Inventor： Claudio Giaccio , Ferdinando Pascale , Raffaele Mastrangelo , Erminio Di Martino , Ferdinando D'Alessandro , Cristiano Castellano , Andrea Castaldo
IPC: G11C29/50
Abstract: Apparatus and methods are disclosed, including test systems for memory devices. Example test systems and methods include power loss logic to determine when one or more test conditions have been met in a memory operation between a host device and a memory device under test. Example test systems and methods include a function to then instruct a power management device to trigger a power loss event.
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公开(公告)号：US11282553B2
公开(公告)日：2022-03-22
申请号：US16731947
申请日：2019-12-31
Applicant: Micron Technology, Inc.
Inventor： Claudio Giaccio , Ferdinando Pascale , Erminio Di Martino , Raffaele Mastrangelo , Ferdinando D'Alessandro , Andrea Castaldo , Cristiano Castellano
Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.
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公开(公告)号：US20200005840A1
公开(公告)日：2020-01-02
申请号：US16022351
申请日：2018-06-28
Applicant: Micron Technology, Inc.
Inventor： Claudio Giaccio , Ferdinando Pascale , Erminio Di Martino , Raffaele Mastrangelo , Ferdinando D'Alessandro , Andrea Castaldo , Cristiano Castellano
Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.
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公开(公告)号：US20200004289A1
公开(公告)日：2020-01-02
申请号：US16022307
申请日：2018-06-28
Applicant: Micron Technology, Inc.
Inventor： Claudio Giaccio , Ferdinando Pascale , Erminio Di Martino , Raffaele Mastrangelo , Ferdinando D'Alessandro , Andrea Castaldo , Cristiano Castellano
IPC: G06F1/12
Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.
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