公开(公告)号：US20240268093A1

公开(公告)日：2024-08-08

申请号：US18435212

申请日：2024-02-07

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Jieun Lee ,  Andrea Gotti ,  Kai Yen Lo ,  David McShannon ,  Daniel Rave ,  Silvia Borsari ,  Hsiao Wei Liu

IPC: H10B12/00

CPC classification number: H10B12/033 ,  H10B12/315

Abstract: A method used in forming an array of capacitors comprises forming a stack comprising sacrificial material and insulative material that is between a top and a bottom of the sacrificial material. The insulative material at least predominately comprises at least one of a silicon nitride, a silicon boronitride, and a silicon carbonitride. Horizontally-spaced openings are formed partially through the sacrificial material. A lining is deposited within the horizontally-spaced openings and directly above the sacrificial material. After depositing the lining, the horizontally-spaced openings are extended through remaining of the sacrificial material. The extended horizontally-spaced openings extend through the insulative material. The insulative material with extended horizontally-spaced openings there-through comprises an insulative horizontal lattice. First capacitor electrodes are formed that are individually within individual of the extended horizontally-spaced openings laterally over the lining that is in the extended horizontally-spaced openings. The sacrificial material is removed and forms a capacitor insulator over the first capacitor electrodes and the insulative horizontal lattice. Second-capacitor-electrode material is formed over the capacitor insulator. Structure independent of method is disclosed