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公开(公告)号：US20230113960A1
公开(公告)日：2023-04-13
申请号：US17499709
申请日：2021-10-12
摘要： Methods, systems, and devices for techniques for manufacturing a double electrode memory array are described. A memory device may be fabricated using a sequence of fabrication steps that include depositing a first stack of materials including a conductive layer, an interface layer, and a first electrode layer. The first stack of materials may be etched to form a first set of trenches. A second stack of materials may be deposited on top of the first stack of materials. The second stack may include a second electrode layer in contact with the first electrode layer, a storage layer, and a third electrode layer. The second stack of materials may be etched to form a second set of trenches above the first set of trenches, and filled with a sealing layer and a dielectric material. The sealing layer may not extend substantially into the first set of trenches.
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公开(公告)号：US20220165333A1
公开(公告)日：2022-05-26
申请号：US17101846
申请日：2020-11-23
发明人： Nicola Ciocchini , Andrea Gotti
摘要： Systems, methods, and apparatus related to dynamically determining read voltages used in memory devices. In one approach, a memory device has a memory array including memory cells. One or more resistors are formed as part of the memory array. A memory controller increments a counter as write operations are performed on the memory cells. When the counter reaches a limit, a write operation is performed on the resistors. The write operation applies voltages to the resistors similarly as applied to the memory cells over time during normal operation. When performing a read operation, a current is applied to one or more of the resistors to determine a boost voltage. When reading the memory cells, a read voltage is adjusted based on the boost voltage. The memory cells are read using the adjusted read voltage.
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3.发明授权公开(公告)号：US10651381B2
公开(公告)日：2020-05-12
申请号：US16040515
申请日：2018-07-19
摘要： Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, a second electrode portion is coupled to the second chalcogenide structure, and a third electrode portion is between the first and second electrode portions. A first portion of an electrically conductive barrier material is disposed between the first and third electrode portions. A second portion of the electrically conductive barrier material is disposed between the second and third electrode portions.
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4.发明申请公开(公告)号：US20180331287A1
公开(公告)日：2018-11-15
申请号：US16045550
申请日：2018-07-25
CPC分类号： H01L45/1608 , H01L27/2427 , H01L27/2463 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/141 , H01L45/144
摘要： Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.
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5.发明授权Phase change memory cells including nitrogenated carbon materials, and related methods 有权包括含氮碳材料的相变记忆单元及相关方法公开(公告)号：US09299929B2
公开(公告)日：2016-03-29
申请号：US14727106
申请日：2015-06-01
发明人： Andrea Gotti , Luca Fumagalli
IPC分类号： H01L21/8239 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1293 , H01L27/2427 , H01L27/2463 , H01L45/06 , H01L45/1253 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1616 , H01L45/1625
摘要： A phase change memory cell comprising a first chalcogenide compound on a first electrode, a first nitrogenated carbon material directly on the first chalcogenide compound, a second chalcogenide compound directly on the first nitrogenated carbon material, and a second nitrogenated carbon material directly on the second chalcogenide compound and directly on a second electrode. Other phase change memory cells are described. A method of forming a phase change memory cell and a phase change memory device are also described.
摘要翻译： 一种相变存储单元，包括在第一电极上的第一硫族化合物，直接位于第一硫属化物化合物上的第一含氮碳材料，直接位于第一氮化碳材料上的第二硫族化合物，以及直接位于第二硫族化物上的第二含氮碳材料 化合物并直接在第二电极上。 其他相变存储单元被描述。 还描述了形成相变存储单元和相变存储器件的方法。
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公开(公告)号：US09257431B2
公开(公告)日：2016-02-09
申请号：US14036788
申请日：2013-09-25
IPC分类号： H01L27/105 , H01L21/28 , H01L21/3213 , H01L45/00 , H01L27/24 , H01L27/22
CPC分类号： H01L45/124 , H01L21/28 , H01L21/3213 , H01L27/1052 , H01L27/222 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/16 , H01L45/1675
摘要： Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.
摘要翻译： 提供了存储单元结构及其形成方法。 示例性存储器单元可以包括开关元件和存储元件。 在存储元件和开关元件之间形成中间电极。 在除了存储元件和开关元件之外的位置处，在开关元件或存储元件附近形成外部电极。 中间电极的横向尺寸不同于外部电极的横向尺寸。
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公开(公告)号：US11373705B2
公开(公告)日：2022-06-28
申请号：US17101846
申请日：2020-11-23
发明人： Nicola Ciocchini , Andrea Gotti
摘要： Systems, methods, and apparatus related to dynamically determining read voltages used in memory devices. In one approach, a memory device has a memory array including memory cells. One or more resistors are formed as part of the memory array. A memory controller increments a counter as write operations are performed on the memory cells. When the counter reaches a limit, a write operation is performed on the resistors. The write operation applies voltages to the resistors similarly as applied to the memory cells over time during normal operation. When performing a read operation, a current is applied to one or more of the resistors to determine a boost voltage. When reading the memory cells, a read voltage is adjusted based on the boost voltage. The memory cells are read using the adjusted read voltage.
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公开(公告)号：US20210126193A1
公开(公告)日：2021-04-29
申请号：US16665679
申请日：2019-10-28
IPC分类号： H01L45/00
摘要： An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.
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公开(公告)号：US10777743B2
公开(公告)日：2020-09-15
申请号：US15792842
申请日：2017-10-25
IPC分类号： H01L45/00 , H01L27/105 , H01L21/28 , H01L27/24 , H01L27/22 , H01L21/3213
摘要： Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.
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10.发明授权公开(公告)号：US10069069B2
公开(公告)日：2018-09-04
申请号：US15848477
申请日：2017-12-20
摘要： Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, a second electrode portion is coupled to the second chalcogenide structure, and a third electrode portion is between the first and second electrode portions. A first portion of an electrically conductive barrier material is disposed between the first and third electrode portions. A second portion of the electrically conductive barrier material is disposed between the second and third electrode portions.
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