公开(公告)号：US20250088200A1

公开(公告)日：2025-03-13

申请号：US18958870

申请日：2024-11-25

Applicant: Micron Technology, Inc.

Inventor： Steven J. Baumgartner ,  Neeraj Savla

IPC: H03M1/78 ,  H03F3/45

Abstract: Various embodiments of the present disclosure relate to apparatuses and methods for control loop circuitry. An interface circuit can comprise a digital to analog converter (DAC) configured to provide a differential output signal, a first control loop portion configured to receive a gain reference voltage and to output a first bias voltage to the DAC; and a second control loop portion configured to receive a common mode voltage of a differential input signal and to output a second bias voltage to the DAC.

公开(公告)号：US20230396266A1

公开(公告)日：2023-12-07

申请号：US17892760

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Steven J. Baumgartner ,  Neeraj Savla

IPC: H03M1/78 ,  H03F3/45

CPC classification number: H03M1/785 ,  H03F3/45179

Abstract: Various embodiments of the present disclosure relate to apparatuses and methods for control loop circuitry. An interface circuit can comprise a digital to analog converter (DAC) configured to provide a differential output signal, a first control loop portion configured to receive a gain reference voltage and to output a first bias voltage to the DAC; and a second control loop portion configured to receive a common mode voltage of a differential input signal and to output a second bias voltage to the DAC.

公开(公告)号：US12155397B2

公开(公告)日：2024-11-26

申请号：US17892760

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Steven J. Baumgartner ,  Neeraj Savla

IPC: H03M1/78 ,  H03F3/45

Abstract: Various embodiments of the present disclosure relate to apparatuses and methods for control loop circuitry. An interface circuit can comprise a digital to analog converter (DAC) configured to provide a differential output signal, a first control loop portion configured to receive a gain reference voltage and to output a first bias voltage to the DAC; and a second control loop portion configured to receive a common mode voltage of a differential input signal and to output a second bias voltage to the DAC.